| 2025 | ISCAS | Live Demonstration: AI-based System Latchup Detection and Protection for COTS Systems. | Yin Sun, Junkai Zhao, Rouli Fang, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang |
| 2025 | ISCAS | N-MUX: Neighborhood-Based Logic Locking Against Machine Learning Attacks. | Han Zhang, Xuenong Hong, Shirui Sheng, Juncheng Chen, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee |
| 2025 | ISCAS | An Adaptive AI-based Approach to Detect and Protect COTS Systems against Micro-Single-Event-Latchups (μ-SELs) and SELs. | Junkai Zhao, Yin Sun, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang |
| 2024 | ISCAS | A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix. | Juncheng Chen, Han Zhang, Zishuo Yang, Yicheng Xu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee |
| 2023 | ISCAS | Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs. | Jun-Sheng Ng, Juncheng Chen, Si Wu, Nay Aung Kyaw, Kwen-Siong Chong, Zhiping Lin, Bah-Hwee Gwee |
| 2022 | ISCAS | Non-profiling based Correlation Optimization Deep Learning Analysis. | Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee |
| 2022 | ISCAS | An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations. | Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee |
| 2021 | ISCAS | Normalized Differential Power Analysis - for Ghost Peaks Mitigation. | Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee |
| 2020 | ISCAS | Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller. | Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Wei Shu, Joseph S. Chang |
| 2020 | ISCAS | A Secure Data-Toggling SRAM for Confidential Data Protection. | Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee |
| 2020 | ISCAS | A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications. | Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2020 | ISCAS | A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES). | Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee |
| 2019 | ISCAS | Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design. | Aparna Shreedhar, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, L. Nalangilli, Wei Shu, Joseph S. Chang, Bah-Hwee Gwee |
| 2017 | ISCAS | DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer. | James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee |
| 2017 | ISCAS | Highly secured state-shift local clock circuit to countermeasure against side channel attack. | Ali Akbar Pammu, Kwen-Siong Chong, Bah-Hwee Gwee |
| 2016 | DATE | Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications. | Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang |
| 2016 | ISCAS | High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. | Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
| 2016 | ISCAS | Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM. | Weng-Geng Ho, Kyaw Zwa Lwin Ne, N. Prashanth Srinivas, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee |
| 2016 | ISCAS | Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process. | Jize Jiang, Wei Shu, Kwen-Siong Chong, Tong Lin, Ne Kyaw Zwa Lwin, Joseph Sylvester Chang, Jingyuan Liu |
| 2016 | ISCAS | Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. | Tong Lin, Kwen-Siong Chong, Wei Shu, Ne Kyaw Zwa Lwin, Jize Jiang, Joseph S. Chang |
| 2015 | ISCAS | High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC). | Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang |
| 2015 | ISCAS | A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. | Rong Zhou, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang |
| 2014 | ISCAS | Synthesis of asynchronous QDI circuits using synchronous coding specifications. | Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho |
| 2013 | ISCAS | A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. | Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2013 | ISCAS | Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. | Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2012 | ISCAS | A comparative study on asynchronous Quasi-Delay-Insensitive templates. | Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2012 | ISCAS | An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. | Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
| 2012 | ISCAS | Energy-delay efficient asynchronous-logic 1616-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. | Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang |
| 2011 | ISCAS | A low-power dual-rail inputs write method for bit-interleaved memory cells. | Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
| 2011 | ISCAS | Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation. | Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang |
| 2009 | ISCAS | Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. | Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
| 2007 | ISCAS | A Low Energy FFT/IFFT Processor for Hearing Aids. | Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
| 2005 | ISCAS | Low-voltage micropower multipliers with reduced spurious switching. | Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
| 2004 | ISCAS | A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. | Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
| 2002 | ISCAS | Low-voltage micropower asynchronous multiplier for hearing instruments. | Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
| 2002 | ISCAS | Low-voltage asynchronous adders for low power and high speed applications. | Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |