| 2026 | ASPLOS | Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits. | Yann Herklotz, Ayatallah Elakhras, Martina Camaioni, Paolo Ienne, Lana Josipovic, Thomas Bourgeat |
| 2026 | FPGA | EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS. | Shun Katsumi, Emmet Murphy, Lana Josipovic |
| 2026 | FPGA | HACE: HLS-Tool-Agnostic CDFG Extraction from RTL Designs. | Carmine Rizzi, Sebastian Pfeiler, Lana Josipovic |
| 2025 | ASPLOS | ElasticMiter: Formally Verified Dataflow Circuit Rewrites. | Ayatallah Elakhras, Jiahui Xu, Martin Erhart, Paolo Ienne, Lana Josipovic |
| 2025 | ASPLOS | CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS. | Jiahui Xu, Lana Josipovic |
| 2025 | DATE | SimGen: Simulation Pattern Generation for Efficient Equivalence Checking. | Carmine Rizzi, Sarah Brunner, Alan Mishchenko, Lana Josipovic |
| 2025 | FCCM | DRSA: Accelerating Macro Placement on Commercial FPGAs. | Menzo Bouaissi, Paolo Ienne, Lana Josipovic, Andrea Guerrieri |
| 2025 | FPL | Compile in Seconds and Run on an FPGA with DynaRapid. | Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne |
| 2025 | ICCAD | Promise: Property Mining for Sequential Synthesis. | Jiahui Xu, Jordi Cortadella, Lana Josipovic |
| 2025 | ISCA | OptiPIM: Optimizing Processing-in-Memory Acceleration Using Integer Linear Programming. | Jiantao Liu, Minxuan Zhou, Yue Pan, Chien-Yi Yang, Lana Josipovic, Tajana Rosing |
| 2024 | FPGA | Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. | Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne |
| 2024 | FPGA | DynaRapid: From C to FPGA in a Few Seconds. | Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne |
| 2024 | FPGA | Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing. | Jiahui Xu, Lana Josipovic |
| 2024 | FPL | DynaRapid: Fast-Tracking from C to Routed Circuits. | Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne |
| 2024 | FPL | Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits. | Jiantao Liu, Maksymilian Graczyk, Andrea Guerrieri, Lana Josipovic |
| 2024 | ICCAD | Balor: HLS Source Code Evaluator Based on Custom Graphs and Hierarchical GNNs. | Emmet Murphy, Lana Josipovic |
| 2023 | DAC | An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits. | Carmine Rizzi, Andrea Guerrieri, Lana Josipovic |
| 2023 | FPGA | Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. | Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne |
| 2023 | FPGA | Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. | Jiahui Xu, Emmet Murphy, Jordi Cortadella, Lana Josipovic |
| 2023 | ICCAD | MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization. | Hanyu Wang, Carmine Rizzi, Lana Josipovic |
| 2023 | ICCAD | Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification. | Jiahui Xu, Lana Josipovic |
| 2022 | FCCM | Resource Sharing in Dataflow Circuits. | Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne |
| 2022 | FPL | Dynamic Inter-Block Scheduling for HLS. | Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson |
| 2022 | FPL | Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. | Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne |
| 2022 | FPL | A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. | Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic |
| 2021 | FPGA | Resource Sharing in Dataflow Circuits. | Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne |
| 2020 | FPGA | Combining Dynamic & Static Scheduling in High-level Synthesis. | Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson |
| 2020 | FPGA | Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. | Lana Josipovic, Andrea Guerrieri, Paolo Ienne |
| 2020 | FPGA | Buffer Placement and Sizing for High-Performance Dataflow Circuits. | Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella |
| 2019 | FPGA | Speculative Dataflow Circuits. | Lana Josipovic, Andrea Guerrieri, Paolo Ienne |
| 2018 | FPGA | Dynamically Scheduled High-level Synthesis. | Lana Josipovic, Radhika Ghosal, Paolo Ienne |
| 2017 | ACSSC | From C to elastic circuits. | Lana Josipovic, Philip Brisk, Paolo Ienne |
| 2017 | FCCM | An Out-of-Order Load-Store Queue for Spatial Computing. | Lana Josipovic, Philip Brisk, Paolo Ienne |