Leendert M. Huisman
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
3
Active years
1983–2004
Best venue rank
A*
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | ITC | Data Mining Integrated Circuit Fails with Fail Commonalities. | Leendert M. Huisman, Maroun Kassab, Leah Pastel |
| 2003 | VTS | Analysis and Design of Optimal Combinational Compactors. | Peter Wohl, Leendert M. Huisman |
| 2001 | ITC | Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. | Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski |
| 1998 | ITC | Correlations between path delays and the accuracy of performance prediction. | Leendert M. Huisman |
| 1998 | ITC | Diagnosis and characterization of timing-related defects by time-dependent light emission. | Daniel R. Knebel, Pia N. Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika |
| 1994 | ITC | The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. | Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman |
| 1992 | ITC | A Small Test Generator for Large Designs. | Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy |
| 1990 | ITC | Fault simulation of logic designs on parallel processors with distributed memory. | Leendert M. Huisman, Raja Daoud |
| 1986 | DAC | SLS - a fast switch level simulator for verification and fault coverage analysis. | Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman |
| 1986 | ITC | TRIM : Testability Range by Ignoring the Memory. | Leendert M. Huisman, Larry Carter, Tom W. Williams |
| 1983 | DAC | Simulating pass transistor circuits using logic simulation machines. | Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo |