Letcia Maria Veiras Bolzani
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
19
Venues
9
Active years
2003–2025
Best venue rank
C
Where they publish
Papers
19 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | IOLTS | ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators. | Jianan Wen, Andrea Baroni, Alberto Mistroni, Eduardo Prez, Cristian Zambelli, Christian Wenger, Milos Krstic, Letcia Maria Veiras Bolzani |
| 2023 | DDECS | Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing? | Letcia Maria Veiras Bolzani |
| 2022 | ETS | Hierarchical Memory Diagnosis. | Guilherme Cardoso Medeiros, Moritz Fieback, Anteneh Gebregiorgis, Mottaqiallah Taouil, Letcia Maria Veiras Bolzani, Said Hamdioui |
| 2013 | IOLTS | Integrating embedded test infrastructure in SRAM cores to detect aging. | W. Prates, Letcia Maria Veiras Bolzani, Gurgen Harutyunyan, A. Davtyan, Fabian Vargas, Yervant Zorian |
| 2011 | ETS | A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded Systems. | Dhiego Silva, Kleber Stangherlin, Letcia Maria Veiras Bolzani, Fabian Vargas |
| 2011 | IOLTS | An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems. | Dhiego Silva, Letcia Maria Veiras Bolzani, Fabian Vargas |
| 2010 | DSD | Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments. | Felipe Lavratti, Alex R. Pinto, Letcia Maria Veiras Bolzani, Fabian Vargas, Carlos Barros Montez, Fernando Hernandez, Edmundo Gatti, C. Silva |
| 2010 | IOLTS | Investigating the Use of BICS to detect resistive-open defects in SRAMs. | Raul Chipana, Letcia Maria Veiras Bolzani, Fabian Vargas, Jorge Semio, Juan J. Rodrguez-Andina, Isabel C. Teixeira, Joo Paulo Teixeira |
| 2009 | DATE | Enabling concurrent clock and power gating in an industrial design flow. | Letcia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2009 | ISCAS | Placement-aware Clustering for Integrated Clock and Power Gating. | Letcia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2008 | DSD | Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. | Enrico Macii, Letcia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino |
| 2007 | CEC | Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores. | Letcia Maria Veiras Bolzani, Ernesto Snchez, Massimiliano Schillaci, Giovanni Squillero |
| 2007 | DDECS | Extended Fault Detection Techniques for Systems-on-Chip. | Paolo Bernardi, Letcia Maria Veiras Bolzani, Matteo Sonza Reorda |
| 2007 | GECCO | Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores. | Letcia Maria Veiras Bolzani, Ernesto Snchez, Massimiliano Schillaci, Giovanni Squillero |
| 2007 | IOLTS | A Hybrid Approach to Fault Detection and Correction in SoCs. | Paolo Bernardi, Letcia Maria Veiras Bolzani, Matteo Sonza Reorda |
| 2007 | IOLTS | An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. | Letcia Maria Veiras Bolzani, Ernesto Snchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero |
| 2005 | DSN | On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. | Paolo Bernardi, Letcia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante |
| 2004 | IOLTS | Hybrid Soft Error Detection by Means of Infrastructure IP Cores. | Letcia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante |
| 2003 | IOLTS | Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? | Fabian Vargas, Diogo B. Brum, Drcio Prestes, Letcia Maria Veiras Bolzani, Eduardo Luis Rhod, Matteo Sonza Reorda |