| 2021 | COMSNETS | Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. | Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, J. Soumya, M. B. Srinivas, Phaneendra K. Yalavarthy, Abhinav Kumar, V. Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi |
| 2018 | VLSID | An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. | Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni, M. B. Srinivas |
| 2017 | RC | Optimizing the Reversible Circuits Using Complementary Control Line Transformation. | Sai Phaneendra Parlapalli, Chetan Kumar Vudadha, M. B. Srinivas |
| 2017 | RC | An ESOP Based Cube Decomposition Technique for Reversible Circuits. | Sai Phaneendra Parlapalli, Chetan Kumar Vudadha, M. B. Srinivas |
| 2017 | VLSID | A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp. | Anjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas |
| 2016 | ARITH | An Iterative Logarithmic Multiplier with Improved Precision. | Syed Ershad Ahmed, Sanket Kadam, M. B. Srinivas |
| 2016 | VLSID | A Hybrid Energy Efficient Digital Comparator. | Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas |
| 2014 | VLSID | An Optimized Design of Reversible Quantum Comparator. | P. Sai Phaneendra, Chetan Kumar Vudadha, Sreehari Veeramachaneni, M. B. Srinivas |
| 2014 | VLSID | A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. | B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas |
| 2014 | VLSID | A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. | Ch. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas |
| 2012 | VLSID | Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. | Chetan Kumar Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas |
| 2011 | DSD | A Unified Architecture for BCD and Binary Adder/Subtractor. | Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas |
| 2010 | VLSID | An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. | Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas |
| 2009 | IWCMC | Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks. | Vasanth Iyer, S. Sitharama Iyengar, Garimella Rama Murthy, Bertrand Hochet, Vir V. Phoha, M. B. Srinivas |
| 2009 | VLSID | Design of a Low Power, Variable-Resolution Flash ADC. | Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas |
| 2008 | VLSID | A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. | Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas |
| 2007 | DSD | A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. | J. V. R. Ravindra, M. B. Srinivas |
| 2007 | GLOBECOM | Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio. | Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas |
| 2007 | ISCAS | Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). | Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas |
| 2007 | ISCAS | Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. | Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas |
| 2007 | VLSID | A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n). | M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas |
| 2007 | VLSID | Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. | Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas |
| 2006 | AICCSA | Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. | Himanshu Thapliyal, Neela Gopi, K. K. Pavan Kumar, M. B. Srinivas |
| 2006 | AICCSA | Novel Reversible Multiplier Architecture Using Reversible TSG Gate. | Himanshu Thapliyal, M. B. Srinivas |
| 2006 | DSD | An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). | Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas |
| 2006 | ISCAS | A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. | K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas |
| 2006 | VLSID | Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. | Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas |
| 2005 | ICNC | A 32-Bit Binary Floating Point Neuro-Chip. | Keerthi Laal Kala, M. B. Srinivas |
| 2003 | ASPDAC | Speech encoding and encryption in VLSI. | K. Kalyan Chakravarthy, M. B. Srinivas |
| 2003 | ASPDAC | Design of a digital CDMA receiver. | I. Vijay Kumar, M. B. Srinivas |