Ma Jos Canet
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
2003–2015
Best venue rank
B
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | ISCAS | A 630 Mbps non-binary LDPC decoder for FPGA. | Jesus Omar Lacruz, Francisco Garcia-Herrero, Ma Jos Canet, Javier Valls, Asuncion Perez-Pascual |
| 2004 | FPL | Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. | Ma Jos Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima |
| 2004 | PIMRC | A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. | Ma Jos Canet, Felip Vicedo, Vicen Almenar, Javier Valls, Eduardo R. de Lima |
| 2003 | FPL | DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. | Jos Marn-Roig, Vicente Torres-Carot, Ma Jos Canet, Asuncion Perez-Pascual, Trinidad Sansaloni, Francisco Cardells-Tormo, Fabian Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat |