Manuel J. Bellido
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
1993–2009
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | FPL | Efficient techniques and methodologies for embedded system design usign free hardware and open standards. | Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido |
| 2001 | DATE | HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. | Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero |
| 2001 | ISCAS | Gate-level simulation of CMOS circuits using the IDDM model. | Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero |
| 2000 | ISCAS | Inertial and degradation delay model for CMOS logic gates. | Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia |
| 1993 | ISCAS | A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. | Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, Jos Luis Huertas, Rafael Domnguez-Castro |