| 2016 | FPL | Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off. | Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski |
| 2014 | CHES | ICEPOLE: High-Speed, Hardware-Oriented Authenticated Encryption. | Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wjcik |
| 2014 | FPL | A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs. | Marcin Rogawski, Ekawat Homsirikamol, Kris Gaj |
| 2012 | DSD | A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grstl. | Marcin Rogawski, Kris Gaj |
| 2011 | CHES | Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. | Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj |
| 2010 | CHES | Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. | Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski |
| 2010 | FPL | ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. | Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster |