| 2025 | ISCAS | Non-Volatile Content-Addressable Memory For Energy-Efficient & High-Performance Search And Update Operations. | Alessandro Bedoya, Benjamin Zambrano, Ramiro Taco, Luis-Miguel Prcel, Marco Lanuzza, Esteban Garzn |
| 2025 | ISCAS | Low Matchline Voltage Swing Content-Addressable Memory Cell. | Cristhopher Mosquera, Ramiro Taco, Benjamin Zambrano, Luis-Miguel Procel, Esteban Garzn, Marco Lanuzza |
| 2025 | ISCAS | Towards Low-Power High-Performance Content-Addressable Memory: A Robust Precharge-Free Approach. | Ramiro Taco, Esteban Garzn, Adam Teman, Leonid Yavits, Marco Lanuzza |
| 2025 | ISCAS | A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider. | Massimo Vatalaro, Raffaele De Rose, Vincenzo Maccaronio, Marco Lanuzza, Felice Crupi |
| 2022 | ISCA | EDAM: edit distance tolerant approximate matching content addressable memory. | Robert Hanhan, Esteban Garzn, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits |
| 2022 | ISCAS | A RISC-V-based Research Platform for Rapid Design Cycle. | Esteban Garzn, Roman Golman, Odem Harel, Tzachi Noy, Yehuda Kra, Asaf Pollock, Slava Yuzhaninov, Yonatan Shoshan, Yehuda Rudin, Yoav Weizman, Marco Lanuzza, Adam Teman |
| 2021 | ISCAS | Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. | Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish |
| 2021 | ISCAS | Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. | Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish |
| 2020 | ISCAS | Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. | Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish |
| 2020 | ISCAS | Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. | Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish |
| 2019 | ISCAS | Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 88-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. | Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish |
| 2017 | ISCAS | A variation-aware simulation framework for hybrid CMOS/spintronic circuits. | Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto |
| 2017 | ISCAS | Evaluation of Dual Mode Logic in 28nm FD-SOI technology. | Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish |
| 2016 | ISCAS | Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology. | Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish |
| 2010 | ISCAS | A new low-power high-speed single-clock-cycle binary comparator. | Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello |
| 2009 | VLSID | Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. | Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala |
| 2007 | DSD | Design and Implementation of a 90nm Low bit-rate Image Compression Core. | Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo |
| 2005 | FPL | Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. | Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello |
| 2005 | ISLPED | Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. | Marco Lanuzza, Martin Margala, Pasquale Corsonello |