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Marco Platzner

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

56

Venues

20

Active years

1995–2026

Best venue rank

A*

Where they publish

Papers

56 indexed papers, newest first.

YearVenueTitleAuthors
2026DDECSDP-MCTS: Deep Playout-Driven MCTS for Approximate Accelerator Design.Muhammad Awais, Hassan Ghasemzadeh Mohammadi, Sayed Morteza Jawadi, Marco Platzner
2026DDECSReliability Assessment in Approximate Accelerator Synthesis.Somayeh Sadeghi Kohan, Muhammad Awais, Qazi Arbab Ahmed, Marco Platzner, Sybille Hellebrand, Thorsten Jungeblut, Hans-Joachim Wunderlich
2026FCCMA Robotics Middleware for FPGAs Supporting Dynamic Function Exchange and Streaming Data Distribution.Alexander Philipp Nowosad, Christian Lienen, Marco Platzner
2025DDECSA Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation.Amir Hossein Hadipour, Atousa Jafari, Muhammad Awais, Marco Platzner
2025DSNDeep&Wide: Achieving Area Efficiency in Scalable Approximate Accelerators.Farjana Jalil, Muhammad Awais, Qazi Arbab Ahmed, Hassan Ghasemzadeh Mohammadi, Thorsten Jungeblut, Marco Platzner
2023IROSFPGADDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications.Christian Lienen, Sorel Horst Middeke, Marco Platzner
2022DACSearch space characterization for approximate logic synthesis.Linus Witschen, Tobias Wiersema, Lucas Reuter, Marco Platzner
2022DATEMUSCAT: MUS-based Circuit Approximation Technique.Linus Witschen, Tobias Wiersema, Matthias Artmann, Marco Platzner
2022DSDEvent-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications.Christian Lienen, Marco Platzner
2022GECCOXCS on embedded systems: an analysis of execution profiles and accelerated classifier deletion.Mathis Brede, Tim Hansmeier, Marco Platzner
2021DATEMalicious Routing: Circumventing Bitstream-level Verification for FPGAs.Qazi Arbab Ahmed, Tobias Wiersema, Marco Platzner
2021GECCOAn experimental comparison of explore/exploit strategies for the learning classifier system XCS.Tim Hansmeier, Marco Platzner
2020ETFADeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep Learning on Embedded Platforms.Hassan Ghasemzadeh Mohammadi, Rahil Arshad, Sneha Rautmare, Suraj Manjunatha, Maurice Kuschel, Felix Paul Jentzsch, Marco Platzner, Alexander Boschmann, Dirk Schollbach
2020GECCOEnabling XCSF to cope with dynamic environments via an adaptive error threshold.Tim Hansmeier, Paul Kaufmann, Marco Platzner
2020GECCOAn adaption mechanism for the error threshold of XCSF.Tim Hansmeier, Paul Kaufmann, Marco Platzner
2017DATEA Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller.Alexander Boschmann, Georg Thombansen, Linus Witschen, Alex Wiens, Marco Platzner
2017DATEAccurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor.Nam Ho, Ishraq Ibne Ashraf, Paul Kaufmann, Marco Platzner
2016DATEPerformance-centric scheduling with task migration for a heterogeneous compute node in the data center.Achim Lsch, Tobias Beisel, Tobias Kenter, Christian Plessl, Marco Platzner
2016DSDBoolean Difference Based Reliability Evaluation of Fault-Tolerant Circuit Structures on FPGAs.Jahanzeb Anwer, Marco Platzner
2016ICSoftNew Co-design Methodology for Real-time Embedded Systems.Ines Ghribi, Riadh Ben Abdallah, Mohamed Khalgui, Marco Platzner
2016ICSoftI-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems.Ines Ghribi, Riadh Ben Abdallah, Mohamed Khalgui, Marco Platzner
2015FPLSignificant papers from the first 25 years of the FPL conference.Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, Joo M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
2014FPLA hardware/software infrastructure for performance monitoring on LEON3 multicore platforms.Nam Ho, Paul Kaufmann, Marco Platzner
2014IFMIntegrating Software and Hardware Verification.Marie-Christine Jakobs, Marco Platzner, Heike Wehrheim, Tobias Wiersema
2013ISORCOn-The-Fly Computing: A novel paradigm for individualized IT services.Markus Happe, Friedhelm Meyer auf der Heide, Peter Kling, Marco Platzner, Christian Plessl
2011EuroParParallel Monte-Carlo Tree Search for HPC Systems.Tobias Graf, Ulf Lorenz, Marco Platzner, Lars Schaefers
2011FPGAPerformance estimation framework for automated exploration of CPU-accelerator architectures.Tobias Kenter, Christian Plessl, Marco Platzner, Michael Kauschke
2011FPLMemory Virtualization for Multithreaded Reconfigurable Hardware.Andreas Agne, Marco Platzner, Enno Lbbers
2010CECA novel hybrid evolutionary strategy and its periodization with multi-objective genetic optimizers.Paul Kaufmann, Tobias Knieper, Marco Platzner
2010FPLA Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.Heiner Giefers, Marco Platzner
2009FCCMIMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.Tobias Schumacher, Christian Plessl, Marco Platzner
2009FPLProgram-driven fine-grained power management for the reconfigurable mesh.Heiner Giefers, Marco Platzner
2009FPLCooperative multithreading in dynamically reconfigurable systems.Enno Lbbers, Marco Platzner
2009FPLAn accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure.Tobias Schumacher, Christian Plessl, Marco Platzner
2008FPLFine grain reconfigurable architectures.Josef Angermeier, Mateusz Majer, Jrgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hbner, Jrgen Becker, Enno Lbbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008FPLA portable abstraction layer for hardware threads.Enno Lbbers, Marco Platzner
2008GECCOAdvanced techniques for the creation and propagation of modules in cartesian genetic programming.Paul Kaufmann, Marco Platzner
2007FPLA Many-core Implementation based on the Reconfigurable Mesh Model.Heiner Giefers, Marco Platzner
2007FPLReconOS: An RTOS supporting Hard- and Software Threads.Enno Lbbers, Marco Platzner
2006FPLExecuting Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions.Klaus Danne, Roland Mhlenbernd, Marco Platzner
2005FPLA Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.Klaus Danne, Marco Platzner
2004FCCMEfficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.Matthias Dyer, Marco Platzner, Lothar Thiele
2004FPLA Runtime Environment for Reconfigurable Hardware Operating Systems.Herbert Walder, Marco Platzner
2003DATEOnline Scheduling for Block-Partitioned Reconfigurable Devices .Herbert Walder, Marco Platzner
2003FPLVirtualizing Hardware with Multi-context Reconfigurable Arrays.Rolf Enzler, Christian Plessl, Marco Platzner
2003FPLHeuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable Devices.Christoph Steiger, Herbert Walder, Marco Platzner
2003RTSSOnline Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices.Christoph Steiger, Herbert Walder, Marco Platzner, Lothar Thiele
2002FCCMCustom Computing Machines for the Set Covering Problem.Christian Plessl, Marco Platzner
2002FPLPartially Reconfigurable Cores for Xilinx Virtex.Matthias Dyer, Christian Plessl, Marco Platzner
2002ISWCReconfigurable Hardware in Wearable Computing Nodes.Christian Plessl, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele
2000FPLOptimization of Run-Time Reconfigurable Embedded Systems.Michael Eisenring, Marco Platzner
2000PDPTAAn Implementation Framework for Run-time Reconfigurable Systems.Michael Eisenring, Marco Platzner
1999FPLCommunication Synthesis for Reconfigurable Embedded Systems.Michael Eisenring, Marco Platzner, Lothar Thiele
1998FPLAcceleration of Satisfiability Algorithms by Reconfigurable Hardware.Marco Platzner, Giovanni De Micheli
1995EuroParA Special-purpose Coprocessor for Qualitative Simulation.Gerald Friedl, Marco Platzner, Bernhard Rinner
1995PDPA distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs.Marco Platzner, Bernhard Rinner, Reinhold Weiss