Masato Motomura
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
28
Venues
18
Active years
1998–2026
Best venue rank
A*
Where they publish
Papers
28 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | AAAI | The Strong Lottery Ticket Hypothesis for Multi-Head Attention Mechanisms. | Hikari Otsuka, Daiki Chijiwa, Yasuyuki Okoshi, Daichi Fujiki, Susumu Takeuchi, Masato Motomura |
| 2026 | HPCA | AQPIM: Breaking the PIM Capacity Wall for LLMs with in-Memory Activation Quantization. | Kosuke Matsushima, Yasuyuki Okoshi, Masato Motomura, Daichi Fujiki |
| 2026 | WACV | Efficient Vision Transformers via Token Merging with Head-Wise Attention Correction. | Yuki Ichikawa, Masato Motomura, Thiem Van Chu, Daichi Fujiki |
| 2025 | ISCA | BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT. | Jiale Yan, Hiroaki Ito, Yuta Nagahara, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki |
| 2024 | ASPDAC | Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. | Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu |
| 2024 | GECCO | Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization. | Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura |
| 2024 | IJCNN | ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data. | Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu |
| 2023 | FCCM | Decision Forest Training Accelerator Based on Binary Feature Decomposition. | Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura |
| 2022 | ICML | Multicoated Supermasks Enhance Hidden Networks. | Yasuyuki Okoshi, ngel Lpez Garca-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu |
| 2021 | BMVC | Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. | ngel Lpez Garca-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu |
| 2020 | ISCAS | A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. | Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda |
| 2019 | DICTA | Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. | Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe |
| 2018 | ICASSP | Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. | Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai |
| 2018 | VCIP | Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. | Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe |
| 2017 | ASPDAC | An image sensor/processor 3D stacked module featuring ThruChip interfaces. | Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura |
| 2017 | FPGA | A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). | Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura |
| 2017 | FPL | FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai |
| 2017 | IJCNN | Exploring optimized accelerator design for binarized convolutional neural networks. | Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura |
| 2017 | ISCAS | Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid |
| 2017 | SGAI | Quantization Error-Based Regularization in Neural Networks. | Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki |
| 2016 | ISCAS | Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid |
| 2014 | FPL | Caching memcached at reconfigurable network interface. | Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura |
| 2011 | FPL | 20Gbps C-Based Complex Event Processing. | Hiroaki Inoue, Takashi Takenaka, Masato Motomura |
| 2004 | FCCM | Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. | Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima |
| 2000 | ASPDAC | Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. | Masakazu Yamashina, Masato Motomura |
| 2000 | FCCM | A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. | Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura |
| 2000 | ICCD | A Study of Channeled DRAM Memory Architectures. | Lars Friebe, Yoshikazu Yabe, Masato Motomura |
| 1998 | FCCM | An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. | Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina |