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Melvin A. Breuer

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

82

Venues

9

Active years

1966–2013

Best venue rank

A*

Where they publish

Papers

82 indexed papers, newest first.

YearVenueTitleAuthors
2013DATEA new paradigm for trading off yield, area and performance to enhance performance per wafer.Yue Gao, Melvin A. Breuer, Yanzhi Wang
2013DATEUsing explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors.Yue Gao, Sandeep K. Gupta, Melvin A. Breuer
2013VTSTrading off area, yield and performance via hybrid redundancy in multi-core architectures.Yue Gao, Yang Zhang, Da Cheng, Melvin A. Breuer
2012ITCA design flow to maximize yield/area of physical devices via redundancy.Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
2010DACHardware that produces bounded rather than exact results.Melvin A. Breuer
2010DATEAlgorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules.Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
2009ITCTolerance of performance degrading faults for effective yield improvement.Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee
2008VTSBasing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER).Zhaoliang Pan, Melvin A. Breuer
2007DATEReduction of detected acceptable faults for yield improvement via error-tolerance.Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2006DATESTAX: statistical crosstalk target set compaction.Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
2006VTSAn Error-Oriented Test Methodology to Improve Yield with Error-Tolerance.Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
2005DSDMulti-media Applications and Imprecise Computation.Melvin A. Breuer
2005ITCMultiple tests for each gate delay fault: higher coverage and lower test application cost.Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
2005ITCA novel test methodology based on error-rate to support error-tolerance.Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer
2004ITCTiming-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models.Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer
2003VTSTest Generation for Maximizing Ground Bounce Considering Circuit Delay.Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
2003VTSAnalyzing Crosstalk in the Presence of Weak Bridge Defects.Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer
2002ICCDAccurate and Efficient Static Timing Analysis with Crosstalk.I-De Huang, Sandeep K. Gupta, Melvin A. Breuer
2002ITCXIDEN: Crosstalk Target Identification Framework.Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
2001DACA New Gate Delay Model for Simultaneous Switching and Its Applications.Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
2001ITCCrosstalk test generation on pseudo industrial circuits: a case study.Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
2001ITCSwitch-level delay test of domino logic circuits.Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
2001VTSTest Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out.Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
2000VLSIDNew Validation and Test Problems for High Performance Deep Submicron VLSI Circuits.Melvin A. Breuer, Sandeep K. Gupta
2000VTSHigh End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability.Melvin A. Breuer
1999ICCADValidation and test generation for oscillatory noise in VLSI interconnects.Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
1999ITCTest generation for crosstalk-induced delay in integrated circuits.Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
1999ITCSwitch-level delay test.Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
1999VTSTest Generation for Ground Bounce in Internal Logic Circuitry.Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
1998DACIntroducing Redundant Computations in a Behavior for Reducing BIST Resources.Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998DATEScheduling and Module Assignment for Reducing Bist Resources.Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1998ITCTest generation in VLSI circuits for crosstalk noise.Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
1997ITCAnalytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs.Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta
1997VTSWill 0.1um Digital Circuits Require Mixed-Signal Testing.Melvin A. Breuer, Bozena Kaminska, John E. McDermid, V. Rayapathi, Donald L. Wheater
1997VTSAnalysis of Ground Bounce in Deep Sub-Micron Circuits.Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
1997VTSHigh Quality Robust Tests for Path Delay Faults.Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
1996DACLower Bounds on Test Resources for Scheduled Data Flow Graphs.Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1996ITCProcess-Aggravated Noise (PAN): New Validation and Test Problems.Melvin A. Breuer, Sandeep K. Gupta
1995DACData Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead.Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
1995VTSAsynchronous multiple scan chain.Sridhar Narayanan, Melvin A. Breuer
1994DACExtraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.Ishwar Parulkar, Melvin A. Breuer, Charles Njinda
1994ITCControl Strategies for Chip-Based DFT/BIST Hardware.Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
1994VTSTest embedding with discrete logarithms.Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer
1993DACAn Efficient Partitioning Strategy for Pseudo-Exhaustive Testing.Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
1993ICCADMerging multiple FSM controllers for DFT/BIST hardware.Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
1993ICCADReconfigurable scan chains: a novel approach to reduce test application time.Sridhar Narayanan, Melvin A. Breuer
1993ITCNovel Test Pattern Generators for Pseudo-Exhaustive Testing.Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
1992DACSWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits.Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
1992ICCADConfiguring multiple scan chains for minimum test time.Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer
1992ITCOptimal Sequencing of Scan Registers.Sridhar Narayanan, Charles Njinda, Melvin A. Breuer
1992VTSTestability properties of acyclic structures and applications to partial scan design.Rajesh Gupta, Melvin A. Breuer
1991ICCADOrdering Storage Elements in a Single Scan Chain.Rajesh Gupta, Melvin A. Breuer
1991ICCADA Systematic Approach for Designing Testable VLSI Circuits.Sen-Pin Lin, Charles Njinda, Melvin A. Breuer
1991ICCADSynthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware.Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer
1991ITCMaximal Diagnosis for Wiring Networks.Jung-Cheun Lien, Melvin A. Breuer
1991VTSConstraints for using IDDQ testing to detect CMOS bridging faults.Kuen-Jong Lee, Melvin A. Breuer
1991VTSA partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing.Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer
1990ICCADA New Method for Assigning Signal Flow Directions to MOS Transistors.Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer
1990ITCObstacles and an approach towards concurrent engineering.Melvin A. Breuer
1990ITCOn the charge sharing problem in CMOS stuck-open fault testing.Kuen-Jong Lee, Melvin A. Breuer
1988ICCADCbase 1.0: a CAD database for VLSI circuits using object oriented technology.Melvin A. Breuer, Wesley H. Cheng, Rajiv Gupta, Ido Hardonag, Ellis Horowitz, S. Y. Lin
1988ICCDFault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor.Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra
1988ICCDThe POTATO chip architecture: a study in tradeoffs for signal processing chip design.B. Sharma, Rajiv Jain, Melvin A. Breuer, Alice C. Parker, Cauligi S. Raghavendra, C. Y. Tseng
1988ITCA Test and Maintenance Controller for a Module Containing Testable Chips.Melvin A. Breuer, Jung-Cheun Lien
1988ITCConcurrent Control of Multiple BIT Structures.Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien
1986ITCScan Path with Look Ahead Shifting (SPLASH).Magdy S. Abadir, Melvin A. Breuer
1985DACA knowledge based system for selecting a test methodology for a PLA.Melvin A. Breuer, Xi-an Zhu
1985DACThe construction of minimal area power and ground nets for VLSI circuits.Salim U. Chowdhury, Melvin A. Breuer
1983DACA placement algorithm for array processors.Dah-Juh Chyan, Melvin A. Breuer
1983DACA module interchange placement machine.Alexander Iosupovicz, Clarence King, Melvin A. Breuer
1982DACA survey of the state-of-the-art of design automation an invited presentation.Melvin A. Breuer
1982DACOptimum placement of two rectangular blocks.Mandalagiri S. Chandrasekhar, Melvin A. Breuer
1982DACOn routing for custom integrated circuits.Zahir A. Syed, Abbas El Gamal, Melvin A. Breuer
1981DACDigital system simulation: Current status and future trends or darwin's theory of simulation.Melvin A. Breuer, Alice C. Parker
1980DACFault diagnosis based on effect-cause analysis: An introduction.Miron Abramovici, Melvin A. Breuer
1979DACIncremental processing applied to Steinberg's placement procedure.Harold W. Carter, Melvin A. Breuer, Zahir A. Syed
1977DACConcurrent fault simulation and functional level modeling.Miron Abramovici, Melvin A. Breuer, K. Kumar
1977DACSome theoretical aspects of algorithmic routing.Prathima Agrawal, Melvin A. Breuer
1977DACA class of min-cut placement algorithms.Melvin A. Breuer
1974DACInitial design concepts for an advanced design automation system.Melvin A. Breuer, Arthur D. Friedman
1968FOCSFault Detection in a Linear Cascade of Identical MachinesMelvin A. Breuer
1966DACThe application of integer programming in design automation.Melvin A. Breuer