Michael Pellauer
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
35
Venues
12
Active years
2005–2026
Best venue rank
A*
Where they publish
Papers
35 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | HPCA | QuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUs. | Nicols Meseguer, Daoxuan Xu, Yifan Sun, Michael Pellauer, Jos L. Abelln, Manuel E. Acacio |
| 2024 | MICRO | FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design. | Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher |
| 2023 | ASPLOS | Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. | Francisco Muoz-Martnez, Raveesh Garg, Michael Pellauer, Jos L. Abelln, Manuel E. Acacio, Tushar Krishna |
| 2023 | ASPLOS | Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. | Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher |
| 2023 | DCC | Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. | Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer |
| 2023 | MICRO | TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. | Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer |
| 2022 | DAC | Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. | Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna |
| 2022 | DATE | DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators. | Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna |
| 2022 | SIGMETRICS | A Formalism of DNN Accelerator Flexibility. | Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna |
| 2021 | HPCA | Heterogeneous Dataflow Accelerators for Multi-DNN Workloads. | Hyoukjun Kwon, Liangzhen Lai, Michael Pellauer, Tushar Krishna, Yu-Hsin Chen, Vikas Chandra |
| 2019 | ASPLOS | Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. | Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer |
| 2019 | MICRO | ExTensor: An Accelerator for Sparse Tensor Algebra. | Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher |
| 2019 | MICRO | Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. | Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna |
| 2018 | DAC | A modular digital VLSI flow for high-productivity SoC design. | Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer |
| 2018 | ISCA | UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition. | Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher |
| 2017 | ASPLOS | TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA. | Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi |
| 2017 | MICRO | RTLcheck: verifying the memory consistency of RTL designs. | Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer |
| 2015 | ISCA | ArMOR: defending against memory consistency model mismatches in heterogeneous architectures. | Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi |
| 2015 | MICRO | CCICheck: using hb graphs to verify the coherence-consistency interface. | Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi |
| 2014 | MICRO | Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models. | Daniel Lustig, Michael Pellauer, Margaret Martonosi |
| 2013 | FPGA | Heracles: a tool for fast RTL-based design space exploration of multicore processors. | Michel A. Kinsy, Michael Pellauer, Srinivas Devadas |
| 2013 | ISCA | Triggered instructions: a control paradigm for spatially-programmed architectures. | Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer |
| 2012 | FPGA | Leveraging latency-insensitivity to ease multiple FPGA design. | Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer |
| 2011 | FPGA | Leap scratchpads: automatic memory and cache management for reconfigurable logic. | Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer |
| 2011 | FPL | Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System. | Michel A. Kinsy, Michael Pellauer, Srinivas Devadas |
| 2011 | HPCA | HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. | Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer |
| 2010 | MEMOCODE | A design flow based on modular refinement. | Nirav Dave, Man Cheuk Ng, Michael Pellauer, Arvind |
| 2010 | MEMOCODE | Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). | Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer |
| 2009 | DAC | Soft connections: addressing the hardware-design modularity problem. | Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer |
| 2008 | FPGA | A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer |
| 2008 | ISPASS | Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer |
| 2007 | MEMOCODE | Scheduling as Rule Composition. | Nirav Dave, Arvind, Michael Pellauer |
| 2007 | MEMOCODE | Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. | Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan |
| 2006 | MEMOCODE | 802.11a transmitter: a case study in microarchitectural exploration. | Nirav Dave, Michael Pellauer, S. Gerding, Arvind |
| 2005 | MEMOCODE | Synthesis of synchronous assertions with guarded atomic actions. | Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil |