| 2024 | ISCAS | Design Automation for Charge Recovery Logic. | Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin |
| 2023 | ISCAS | Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders. | Mineo Kaneko |
| 2022 | ICCD | Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem. | Yuya Ushioda, Mineo Kaneko |
| 2022 | ISCAS | Three-Dimensional Flexible-Module Placement for Stacked Three-Dimensional Integration. | Tomohiro Noguchi, Omran Hindawi, Mineo Kaneko |
| 2021 | ISCAS | Minimum Structural Transformation in Parallel Prefix Adders and its Application to Search-Based Optimization. | Mineo Kaneko |
| 2020 | ISCAS | Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders. | Mineo Kaneko |
| 2019 | ISCAS | A Novel Framework for Procedural Construction of Parallel Prefix Adders. | Mineo Kaneko |
| 2018 | ISCAS | Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing. | Takayuki Moto, Mineo Kaneko |
| 2017 | ISCAS | KKT-condition inspired solution of DVFS with limited number of voltage levels. | Mineo Kaneko |
| 2016 | ISCAS | A 16-valued logic FPGA architecture employing analog memory circuit. | Renyuan Zhang, Mineo Kaneko |
| 2015 | ISCAS | Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis. | Junghoon Oh, Mineo Kaneko |
| 2015 | ISCAS | A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism. | Renyuan Zhang, Mineo Kaneko |
| 2014 | ISCAS | Constrained binding and scheduling of triplicated algorithm for fault tolerant datapath synthesis. | Mineo Kaneko, Yutaka Tsuboishi |
| 2012 | ASPDAC | Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. | Keisuke Inoue, Mineo Kaneko |
| 2012 | ICCD | Timing-test scheduling for constraint-graph based post-silicon skew tuning. | Mineo Kaneko |
| 2012 | ISCAS | Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis. | Keisuke Inoue, Mineo Kaneko |
| 2012 | ISCAS | Post-silicon skew tuning algorithm utilizing setup and hold timing tests. | Mineo Kaneko, Jian Li |
| 2011 | ISCAS | Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis. | Keisuke Inoue, Mineo Kaneko |
| 2009 | ISCAS | Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis. | Takayuki Obata, Mineo Kaneko |
| 2008 | ICCD | Safe clocking register assignment in datapath synthesis. | Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki |
| 2008 | ISCAS | Concurrent skew and control step assignments in RT-level datapath synthesis. | Takayuki Obata, Mineo Kaneko |
| 2007 | ICCAD | Efficient path delay test generation based on stuck-at test generation using checker circuitry. | Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara |
| 2005 | ICCD | Statistical Analysis Driven Synthesis of Asynchronous Systems. | Koji Ohashi, Mineo Kaneko |
| 2005 | ISCAS | Statistical schedule length analysis in asynchronous datapath synthesis. | Koji Ohashi, Mineo Kaneko |
| 2003 | ISCAS | Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism. | Mineo Kaneko, Kazuaki Oshio |
| 2002 | ISCAS | 3D scheduling based on code space exploration for dynamically reconfigurable systems. | Mineo Kaneko, Jun'ichi Yokoyama, Satoshi Tayu |
| 2002 | ISCAS | Heuristic assignment-driven scheduling for data-path synthesis. | Koji Ohashi, Mineo Kaneko |
| 2001 | ISCAS | Extended dimensional threshold filtering-a bridge between FIR filter and median type filter. | Mineo Kaneko, Yasuaki Maekawa |
| 2000 | ICCD | Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. | Koji Ohashi, Mineo Kaneko, Satoshi Tayu |
| 2000 | ISCAS | Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications. | Mineo Kaneko, Yoshitaka Nishio, Satoshi Tayu |
| 2000 | ISCAS | An efficient scheme based on EMPDC graph model in synthesizing fault tolerant FIR filter. | Choon-Sik Park, Mineo Kaneko |
| 1999 | ISCAS | Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power. | Mineo Kaneko |
| 1997 | ICASSP | Adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error with variable forgetting factors. | Fernando Gil Vianna Resende Jr., Paulo S. R. Diniz, Mineo Kaneko, Akinori Nishihara |
| 1994 | ISCAS | Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model. | Mineo Kaneko, Kazuhiro Sakaguchi |
| 1994 | ISCAS | AR Spectrum Estimation Based on Wavelet Representation. | Fernando Gil Resende, Keiichi Tokuda, Mineo Kaneko |
| 1994 | ISCAS | A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach. | Sarwono Sutikno, Mineo Kaneko, Mahoki Onoda |
| 1993 | ISCAS | A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits. | Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi |