| 2025 | ASPDAC | LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference. | Yanyue Xie, Zhengang Li, Dana Diaconu, Suranga Handagala, Miriam Leeser, Xue Lin |
| 2025 | FCCM | Transfer Learning on the Edge for a Wireless Application Using an SoC Platform. | Yiyue Jiang, John Dooley, Aidan Edward Colgan, Jonathan Guimaraes Ribeiro, Zhilin Ren, Miriam Leeser |
| 2024 | FPGA | Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function. | Yiyue Jiang, Andrius Vaicaitis, John Dooley, Miriam Leeser |
| 2024 | INFOCOM | P4-Based In-Network Telemetry for FPGAs in the Open Cloud Testbed and FABRIC. | Sandeep Bal, Zhaoyang Han, Suranga Handagala, Mert Cevik, Michael Zink, Miriam Leeser |
| 2023 | DATE | Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO Systems. | Yiyue Jiang, Andrius Vaicaitis, Miriam Leeser, John Dooley |
| 2023 | INFOCOM | A Framework to Enable Runtime Programmable P4-enabled FPGAs in the Open Cloud Testbed. | Zhaoyang Han, Suranga Handagala, Kalyani Patle, Michael Zink, Miriam Leeser |
| 2022 | DAC | FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results. | Mengshu Sun, Zhengang Li, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang |
| 2022 | FPL | Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization. | Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang |
| 2022 | INFOCOM | Network Attached FPGAs in the Open Cloud Testbed (OCT). | Suranga Handagala, Miriam Leeser, Kalyani Patle, Michael Zink |
| 2020 | DAC | 3D CNN Acceleration on FPGA using Hardware-Aware Pruning. | Mengshu Sun, Pu Zhao, Mehmet Gngr, Massoud Pedram, Miriam Leeser, Xue Lin |
| 2020 | FPGA | Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. | Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle |
| 2019 | SC | Accelerating Large Garbled Circuits on an FPGA-enabled Cloud. | Miriam Leeser, Mehmet Gngr, Kai Huang, Stratis Ioannidis |
| 2018 | FCCM | Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation. | Jieming Xu, Miriam Leeser |
| 2018 | FPL | Digital Pre-distortion Implemented Using FPGA. | Declan Byrne, Ronan Farrell, Sidath Madhuwantha, Miriam Leeser, John Dooley |
| 2018 | PDP | Local and Global Shared Memory for Task Based HPC Applications on Heterogeneous Platforms. | Chao Liu, Miriam Leeser |
| 2017 | FPGA | Secure Function Evaluation Using an FPGA Overlay Architecture. | Xin Fang, Stratis Ioannidis, Miriam Leeser |
| 2017 | FPL | FPGA modeling techniques for detecting and demodulating multiple wireless protocols. | Benjamin Drozdenko, Suranga Handagala, Kaushik R. Chowdhury, Miriam Leeser |
| 2017 | HPDC | Using High Level GPU Tasks to Explore Memory and Communications Options on Heterogeneous Platforms. | Chao Liu, Janki Bhimani, Miriam Leeser |
| 2017 | ICCD | Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. | Michaela Blott, Thomas B. Preuer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser |
| 2017 | PPoPP | A Framework for Developing Parallel Applications with high level Tasks on Heterogeneous Platforms. | Chao Liu, Miriam Leeser |
| 2016 | DCOSS | State-Action Based Link Layer Design for IEEE 802.11b Compliant MATLAB-Based SDR. | Ramanathan Subramanian, Eric Doyle, Benjamin Drozdenko, Miriam Leeser, Kaushik R. Chowdhury |
| 2016 | FPL | Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers. | Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser |
| 2016 | INFOCOM | High-level hardware-software co-design of an 802.11a transceiver system using Zynq SoC. | Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Miriam Leeser, Kaushik R. Chowdhury |
| 2016 | IPCCC | Performance prediction techniques for scalable large data processing in distributed MPI systems. | Janki Bhimani, Ningfang Mi, Miriam Leeser |
| 2015 | EuroPar | Behavioral Non-portability in Scientific Numeric Computing. | Yijia Gu, Thomas Wahl, Mahsa Bayati, Miriam Leeser |
| 2015 | ISCA | Side-channel analysis of MAC-Keccak hardware implementations. | Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, David R. Kaeli, Miriam Leeser |
| 2014 | DATE | Make it real: Effective floating-point reasoning via exact arithmetic. | Miriam Leeser, Saoni Mukherjee, Jaideep Ramachandran, Thomas Wahl |
| 2014 | FCCM | Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework. | Jonathon Pendlum, Miriam Leeser, Kaushik R. Chowdhury |
| 2013 | FPGA | Minimum energy operation for clustered island-style FPGAs. | Peter Grossmann, Miriam Leeser, Marvin Onabajo |
| 2012 | FCCM | Cognitive Radio Universal Software Hardware. | George Eichinger, Kaushik R. Chowdhury, Miriam Leeser |
| 2012 | FCCM | Implementing Murf: Accelerating Large State Space Exploration on FPGAs. | Mary Ellen Tie, Miriam Leeser |
| 2012 | FPGA | Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation. | Scott Bailie, Miriam Leeser |
| 2012 | FPL | CRUSH: Cognitive Radio Universal Software Hardware. | George Eichinger, Kaushik R. Chowdhury, Miriam Leeser |
| 2011 | FCCM | An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs. | Jainik Kathiara, Miriam Leeser |
| 2011 | FPGA | A prototype FPGA for subthreshold-optimized CMOS (abstract only). | Peter Grossmann, Miriam Leeser |
| 2009 | ASPLOS | Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA. | Perhaad Mistry, Sherman Braganza, David R. Kaeli, Miriam Leeser |
| 2008 | FCCM | An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware. | Sherman Braganza, Miriam Leeser |
| 2008 | FCCM | An FPGA Implementation of Explicit-State Model Checking. | Mary Ellen Fuess, Miriam Leeser, Tim Leonard |
| 2008 | FPGA | Efficient FPGA implementation of qr decomposition using a systolic array architecture. | Xiaojun Wang, Miriam Leeser |
| 2008 | SC | Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison. | Sherman Braganza, Miriam Leeser |
| 2007 | FCCM | Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware. | Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King |
| 2007 | FCCM | K-means Clustering for Multispectral Images Using Floating-Point Divide. | Xiaojun Wang, Miriam Leeser |
| 2006 | FCCM | Advanced Components in the Variable Precision Floating-Point Library. | Xiaojun Wang, Sherman Braganza, Miriam Leeser |
| 2006 | FCCM | Automatic Sliding Window Operation Optimization for FPGA-Based. | Haiqian Yu, Miriam Leeser |
| 2006 | FPGA | Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. | Joshua Noseworthy, Miriam Leeser |
| 2006 | SC | Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer. | Ben Cordes, Miriam Leeser, Eric L. Miller, Richard W. Linderman |
| 2005 | FPGA | Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). | Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel |
| 2005 | RSP | Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware. | Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel |
| 2004 | FCCM | Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications. | Miriam Leeser, Shawn Miller, Haiqian Yu |
| 2004 | FPGA | An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. | Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport |
| 2003 | FCCM | Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. | Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis |
| 2002 | FPGA | Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. | Srdjan Coric, Miriam Leeser, Eric L. Miller, Marc Trepanier |
| 2002 | FPL | A Library of Parameterized Floating-Point Modules and Their Use. | Pavle Belanovic, Miriam Leeser |
| 2001 | FPGA | Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. | Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski |
| 2001 | ICCD | Run-Time Execution of Reconfigurable Hardware in a Java Environment. | Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos |
| 2000 | FPGA | Implementing a RAKE receiver for wireless communications on an FPGA-based computer system. | Ali M. Shankiti, Miriam Leeser |
| 1998 | DAC | The DT-Model: High-Level Synthesis Using Data Transfers. | Shantanu Tarafdar, Miriam Leeser |
| 1998 | FCCM | High Level Synthesis for Designing Custom Computing Hardware. | Goran Doncev, Miriam Leeser, Shantanu Tarafdar |
| 1998 | ICCAD | Integrating floorplanning in data-transfer based high-level synthesis. | Shantanu Tarafdar, Miriam Leeser, Zixin Yin |
| 1998 | RSP | Truly Rapid Prototyping Requires High-Level Synthesis. | Goran Doncev, Miriam Leeser, Shantanu Tarafdar |
| 1997 | FPL | Rothko: A three dimensional FPGA architecture, its fabrication, and design tools. | Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Paul M. Zavracky |
| 1997 | ICCD | Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder. | Peter Soderquist, Miriam Leeser |
| 1995 | ARITH | An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. | Peter Soderquist, Miriam Leeser |
| 1995 | ICCD | Verification of a subtractive radix-2 square root algorithm and implementation. | Miriam Leeser, John W. O'Leary |
| 1994 | ICCAD | Simulation of digital circuits in the presence of uncertainty. | Mark H. Linderman, Miriam Leeser |
| 1993 | ICCD | A Framework for Specifying and Designing Pipelines. | Mark D. Aagaard, Miriam Leeser |
| 1992 | CAV | Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification. | Mark D. Aagaard, Miriam Leeser |
| 1991 | ICCD | A Formally Verified System for Logic Synthesis. | Mark D. Aagaard, Miriam Leeser |