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Mirjana Stojilovic

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

26

Venues

7

Active years

2012–2026

Best venue rank

A

Where they publish

Papers

26 indexed papers, newest first.

YearVenueTitleAuthors
2026FCCMPathSteiner: Improving PathFinder with Quasi-Optimal Steiner-Tree Initialization.Shashwat Shrivastava, Luka Kuresevic, Alexandros Poupakis, Chirag Ravishankar, Dinesh Gaitonde, Stefan Nikolic, Mirjana Stojilovic
2026FPGAOut with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS.Rouzbeh Pirayadi, Ayatallah Elakhras, Mirjana Stojilovic, Paolo Ienne
2025FCCMGuaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox.Shashwat Shrivastava, Stefan Nikolic, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2025FPGAFRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis.Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne
2025ICCADFRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs.Louis Coulon, Adham Ragab, Jason Anderson, Mirjana Stojilovic, Paolo Ienne
2023DATETemperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs.Ognjen Glamocanin, Hajira Bazaz, Mathias Payer, Mirjana Stojilovic
2023DDECSActive Wire Fences for Multitenant FPGAs.Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic
2023FPGAMitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2023FPLGRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors.Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson
2023ICCADIIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck.Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2022DATEA Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time.Hedi Fendri, Marco Macchetti, Jrme Perrine, Mirjana Stojilovic
2022DATEFPGA-to-CPU Undervolting Attacks.Dina G. Mahmoud, Samah Hussein, Vincent Lenders, Mirjana Stojilovic
2021DATEShared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks.Ognjen Glamocanin, Dina G. Mahmoud, Francesco Regazzoni, Mirjana Stojilovic
2021FPGANetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs.Morten B. Petersen, Stefan Nikolic, Mirjana Stojilovic
2020DATEAre Cloud FPGAs Really Vulnerable to Power Analysis Attacks?Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic
2020FPGABuilt-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs.Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic
2020FPGACloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors.Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic
2020FPGAClosing Leaks: Routing Against Crosstalk Side-Channel Attacks.Zeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic
2020FPLX-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs.Dina G. Mahmoud, Wei Hu, Mirjana Stojilovic
2020VLSIDA Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer.Frdric Gessler, Philip Brisk, Mirjana Stojilovic
2019DATETiming Violation Induced Faults in Multi-Tenant FPGAs.Dina Mahmoud, Mirjana Stojilovic
2019FPGADesign and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform.Dario Korolija, Mirjana Stojilovic
2019FPLPhysical Side-Channel Attacks and Covert Communication on FPGAs: A Survey.Seyedeh Sharareh Mirzargar, Mirjana Stojilovic
2018FPLDeterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model.Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk
2017FPLParallel FPGA routing: Survey and challenges.Mirjana Stojilovic
2012DATESelective flexibility: Breaking the rigidity of datapath merging.Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne