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Nacer-Eddine Zergainoh

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

33

Venues

9

Active years

1994–2024

Best venue rank

A

Where they publish

Papers

33 indexed papers, newest first.

YearVenueTitleAuthors
2024DATEEnhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification.Nasr-Eddine Ouldei Tebina, Luc Salvo, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri
2023IOLTSRay-Spect: Local Parametric Degradation for Secure Designs: An application to X-Ray Fault Injection.Nasr-Eddine Ouldei Tebina, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri
2018DATEDesigning reliable processor cores in ultimate CMOS and beyond: A double sampling solution.Thierry Bonnoit, Fraidy Bouesse, Nacer-Eddine Zergainoh, Michael Nicolaidis
2018DATEA soft-error resilient route computation unit for 3D Networks-on-Chips.Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan A. Fraire, Raoul Velazco
2017ASPDACDetailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU.Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis
2017ETSRout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs.Amir Charif, Nacer-Eddine Zergainoh, Alexandre Coelho, Michael Nicolaidis
2016ETSAddressing transient routing errors in fault-tolerant Networks-on-Chips.Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis
2015IOLTSMUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip.Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis
2014ETSA generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis.Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis
2014IOLTSPreliminary results of SEU fault-injection on multicore processors in AMP mode.Vanessa Vargas, Pablo Ramos, Wassim Mansour, Raoul Velazco, Nacer-Eddine Zergainoh, Jean-Franois Mhaut
2013ETSVariability-aware and fault-tolerant self-adaptive applications for many-core chips.Gilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis
2013IOLTSVariability-aware and fault-tolerant self-adaptive applications for many-core chips.Gilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis
2013IOLTSFault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip.Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Nicolaidis
2012DATEDesign for test and reliability in ultimate CMOS.Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2011DATEA fault-tolerant deadlock-free adaptive routing for on chip interconnects.Fabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis
2011DATEEliminating speed penalty in ECC protected memories.Michael Nicolaidis, Thierry Bonnoit, Nacer-Eddine Zergainoh
2011ETSEfficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor.Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh
2011ICCDTowards a tool for implementing delay-free ECC in embedded memories.Thierry Bonnoit, Michael Nicolaidis, Nacer-Eddine Zergainoh
2011IOLTSVariability-aware task mapping strategies for many-cores processor chips.Fabien Chaix, Gilles Bizot, Michael Nicolaidis, Nacer-Eddine Zergainoh
2011NCASelf-Recovering Parallel Applications in Multi-core Systems.Gilles Bizot, Dimiter Avresky, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis
2010NCAFault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems.Fabien Chaix, Dimiter Avresky, Nacer-Eddine Zergainoh, Michael Nicolaidis
2009IOLTSVariability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip.Gilles Bizot, Nacer-Eddine Zergainoh, Michael Nicolaidis
2007RSPLow Runtime-Overhead Software Synthesis for Communicating Concurrent Processes.Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya
2007RTCSABuffer Size Reduction through Control-Flow Decomposition.Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi
2005ASPDACScheduler implementation in MP SoC design.Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2005ASPDACIP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems.Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard
2003DATEScheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh
2003RSPAn Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells.Ludovic Tambour, Nacer-Eddine Zergainoh, Pascal Urard, Henri Michel, Ahmed Amine Jerraya
2001DATEAn efficient architecture model for systematic design of application-specific multiprocessor SoC.Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2000ICCDMulti-Level Communication Synthesis of Heterogeneous Multilanguage Specification.Fabiano Hessel, Philippe Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
2000RSPDesign Space Exploration for Hardware/Software Codesign of Multiprocessor Systems.Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesrio, T. Roudier, Ahmed Amine Jerraya
1999RSPCommunication Interface Synthesis for Multilanguage Specifications.Fabiano Hessel, Philippe Coste, P. LeMarrec, Nacer-Eddine Zergainoh, Jean-Marc Daveau, Ahmed Amine Jerraya
1994PDPA Real Time Multiprocessor Application Development Environment Design And Implementation.Nacer-Eddine Zergainoh, Thierry Maurin, Yves Sorel, Christophe Lavarenne