| 2015 | DATE | GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games. | Tony Casagrande, Nagarajan Ranganathan |
| 2014 | VLSID | Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. | Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan |
| 2014 | VLSID | Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. | Matthew Morrison, Nagarajan Ranganathan |
| 2012 | DATE | Mach-Zehnder interferometer based design of all optical reversible binary adder. | Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan |
| 2012 | DATE | Run-time power-gating in caches of GPUs for leakage energy savings. | Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan |
| 2012 | VLSID | Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2010 | VLSID | Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2009 | ICCD | Compiler-directed leakage reduction in embedded microprocessors. | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori |
| 2009 | ISCAS | A VLSI System Architecture for Optical Flow Computation. | Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan |
| 2009 | ISCAS | Exploring Compiler Optimizations for Enhancing Power Gating. | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori |
| 2009 | ISCAS | Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2009 | VLSID | RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. | Koustav Bhattacharya, Nagarajan Ranganathan |
| 2009 | VLSID | Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. | Himanshu Thapliyal, Nagarajan Ranganathan |
| 2008 | ICPR | A microeconomic approach to multi-objective spatial clustering. | Upavan Gupta, Nagarajan Ranganathan |
| 2008 | ISLPED | Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. | Koustav Bhattacharya, Nagarajan Ranganathan |
| 2008 | ISLPED | An expected-utility based approach to variation aware VLSI optimization under scarce information. | Upavan Gupta, Nagarajan Ranganathan |
| 2007 | ICCD | Improving the reliability of on-chip L2 cache using redundancy. | Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan |
| 2007 | IROS | A microeconomic approach to multi-robot team formation. | Upavan Gupta, Nagarajan Ranganathan |
| 2007 | VLSID | A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. | Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan |
| 2006 | VLSID | A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. | Narender Hanchate, Nagarajan Ranganathan |
| 2006 | VLSID | Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. | Aswath Oruganti, Nagarajan Ranganathan |
| 2006 | VLSID | An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. | Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh |
| 2004 | VLSID | A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. | Narender Hanchate, Nagarajan Ranganathan |
| 2004 | VLSID | ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. | Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi |
| 2004 | VLSID | VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. | Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa |
| 1999 | ICASSP | Context modeling of wavelet coefficients in EZW-based lossless image coding. | Veeraraghavan N. Ramaswamy, Kamesh Namuduri, Nagarajan Ranganathan |
| 1998 | ISCC | An adaptive scheme for better utilization with QoS constraints for VBR video traffic in ATM networks. | Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan |
| 1998 | VLSID | A VLSI ATM Switch Architecture for VBR Traffic. | Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu |
| 1996 | HiPC | A linear systolic algorithm and architecture for convex bipartite matching. | Nagarajan Ranganathan, Rajesh Chandra |
| 1996 | ICIP | DFLAP: a dynamic frequency linear array processor. | Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar |