| 2024 | ICCAD | On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks. | Saion K. Roy, Naresh R. Shanbhag |
| 2023 | DATE | PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. | Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo |
| 2023 | ICASSP | Boosting the Accuracy of SRAM-Based in-Memory Architectures Via Maximum Likelihood-Based Error Compensation Method. | Hyungyo Kim, Naresh R. Shanbhag |
| 2023 | ICASSP | Enhancing the Accuracy of Resistive In-Memory Architectures using Adaptive Signal Processing. | Han-Mo Ou, Naresh R. Shanbhag |
| 2023 | ICML | On the Robustness of Randomized Ensembles to Adversarial Perturbations. | Hassan Dbouk, Naresh R. Shanbhag |
| 2022 | ICASSP | IMPQ: Reduced Complexity Neural Networks Via Granular Precision Assignment. | Sujan Kumar Gonugondla, Naresh R. Shanbhag |
| 2022 | ICML | Adversarial Vulnerability of Randomized Ensembles. | Hassan Dbouk, Naresh R. Shanbhag |
| 2022 | ISCAS | Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures. | Saion K. Roy, Ameya Patil, Naresh R. Shanbhag |
| 2021 | ISSRE | Optimizing Selective Protection for CNN Resilience. | Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Christopher W. Fletcher, Sarita V. Adve, Charbel Sakr, Naresh R. Shanbhag, Pavlo Molchanov, Michael B. Sullivan, Timothy Tsai, Stephen W. Keckler |
| 2020 | ECCV | DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. | Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag |
| 2020 | ICASSP | Low-Complexity Fixed-Point Convolutional Neural Networks For Automatic Target Recognition. | Hassan Dbouk, Hanfei Geng, Craig M. Vineyard, Naresh R. Shanbhag |
| 2020 | ICCAD | SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory Computing. | Sujan K. Gonugondla, Ameya D. Patil, Naresh R. Shanbhag |
| 2020 | ICCAD | Fundamental Limits on the Precision of In-memory Architectures. | Sujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag |
| 2019 | ICLR | Per-Tensor Fixed-Point Quantization of the Back-Propagation Algorithm. | Charbel Sakr, Naresh R. Shanbhag |
| 2019 | ICLR | Accumulation Bit-Width Scaling For Ultra-Low Precision Training Of Deep Networks. | Charbel Sakr, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Ankur Agrawal, Naresh R. Shanbhag, Kailash Gopalakrishnan |
| 2019 | ISCAS | An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks. | Ameya D. Patil, Haocheng Hua, Sujan K. Gonugondla, Mingu Kang, Naresh R. Shanbhag |
| 2019 | ISCAS | An Energy-Efficient Classifier via Boosted Spin Channel Networks. | Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag |
| 2018 | ICASSP | True Gradient-Based Training of Deep Binary Activated Neural Networks Via Continuous Binarization. | Charbel Sakr, Jungwook Choi, Zhuo Wang, Kailash Gopalakrishnan, Naresh R. Shanbhag |
| 2018 | ICASSP | An Analytical Method to Determine Minimum Per-Layer Precision of Deep Neural Networks. | Charbel Sakr, Naresh R. Shanbhag |
| 2018 | ISCA | PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms. | Prakalp Srivastava, Mingu Kang, Sujan K. Gonugondla, Sungmin Lim, Jungwook Choi, Vikram S. Adve, Nam Sung Kim, Naresh R. Shanbhag |
| 2018 | ISCAS | Energy-Efficient Deep In-memory Architecture for NAND Flash Memories. | Sujan K. Gonugondla, Mingu Kang, Yongjune Kim, Mark Helm, Sean Eilert, Naresh R. Shanbhag |
| 2018 | ISIT | SRAM Bit-line Swings Optimization using Generalized Waterfilling. | Yongjune Kim, Mingu Kang, Lav R. Varshney, Naresh R. Shanbhag |
| 2017 | DAC | A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. | Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young |
| 2017 | ICASSP | Minimum precision requirements for the SVM-SGD learning algorithm. | Charbel Sakr, Ameya Patil, Sai Zhang, Yongjune Kim, Naresh R. Shanbhag |
| 2017 | ICML | Analytical Guarantees on Numerical Precision of Deep Neural Networks. | Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag |
| 2017 | ISCAS | PredictiveNet: An energy-efficient convolutional neural network via zero prediction. | Yingyan Lin, Charbel Sakr, Yongjune Kim, Naresh R. Shanbhag |
| 2016 | DATE | Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics. | Sai Zhang, Naresh R. Shanbhag |
| 2016 | ICASSP | Analysis of error resiliency of belief propagation in computer vision. | Jungwook Choi, Ameya D. Patil, Rob A. Rutenbar, Naresh R. Shanbhag |
| 2016 | ICASSP | Perfect error compensation via algorithmic error cancellation. | Sujan K. Gonugondla, Byonghyo Shim, Naresh R. Shanbhag |
| 2015 | ICASSP | An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks. | Mingu Kang, Sujan K. Gonugondla, Min-Sun Keel, Naresh R. Shanbhag |
| 2015 | ICCAD | Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels. | Sai Zhang, Naresh R. Shanbhag |
| 2015 | ISCAS | Energy-efficient and high throughput sparse distributed memory architecture. | Mingu Kang, Eric P. Kim, Min-Sun Keel, Naresh R. Shanbhag |
| 2015 | ISLPED | Statistical information processing: Computing for the nanoscale era. | Naresh R. Shanbhag |
| 2014 | ICASSP | A robust message passing based stereo matching kernel via system-level error resiliency. | Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar |
| 2014 | ICASSP | An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM. | Mingu Kong, Min-Sun Keel, Naresh R. Shanbhag, Sean Eilert, Ken Curewitz |
| 2014 | ISLPED | Energy-efficient dot product computation using a switched analog circuit architecture. | Ihab Nahlus, Eric P. Kim, Naresh R. Shanbhag, David T. Blaauw |
| 2013 | ICASSP | Statistical analysis of algorithmic noise tolerance. | Eric P. Kim, Naresh R. Shanbhag |
| 2012 | ACSSC | A sphere decoding approach for the vector Viterbi algorithm. | Peter Kairouz, Aolin Xu, Naresh R. Shanbhag, Andrew C. Singer |
| 2012 | ICASSP | A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems. | Aadithya V. Karthik, Yingyan Lin, Chenjie Gu, Aolin Xu, Jaijeet S. Roychowdhury, Naresh R. Shanbhag |
| 2012 | ICASSP | System-driven metrics for the design and adaptation of analog to digital converters. | Rajan Narasimha, Georg Zeitler, Naresh R. Shanbhag, Andrew C. Singer, Gerhard Kramer |
| 2011 | DATE | Timing error statistics for energy-efficient robust DSP systems. | Rami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag |
| 2011 | DATE | System-assisted analog mixed-signal design. | Naresh R. Shanbhag, Andrew C. Singer |
| 2011 | ICASSP | Least squares approximation and polyphase decomposition for pipelining recursive filters. | Aditya Gupta, Andrew C. Singer, Naresh R. Shanbhag |
| 2011 | ISLPED | System energy minimization via joint optimization of the DC-DC converter and the core. | Rami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein |
| 2010 | DAC | Stochastic computation. | Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones |
| 2010 | ICASSP | Soft NMR: Analysis & application to DSP systems. | Eric P. Kim, Naresh R. Shanbhag |
| 2010 | ICCD | Robust and energy-efficient DSP systems via output probability processing. | Rami A. Abdallah, Naresh R. Shanbhag |
| 2010 | ISCAS | BER-optimal analog-to-digital converters for communication links. | Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer |
| 2009 | GLOBECOM | Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links. | Rajan Narasimha, Nirmal Warke, Naresh R. Shanbhag |
| 2008 | ACSSC | Forward error correction for high-speed I/O. | Rajan Lakshmi Narasimha, Naresh R. Shanbhag |
| 2008 | ICASSP | Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption. | Shrikanth S. Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag |
| 2008 | ISCAS | Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. | Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones |
| 2008 | ISLPED | Error-resilient low-power Viterbi decoders. | Rami A. Abdallah, Naresh R. Shanbhag |
| 2006 | ISLPED | Energy-efficient motion estimation using error-tolerance. | Girish Varatkar, Naresh R. Shanbhag |
| 2005 | ISCAS | An energy-efficient circuit technique for single event transient noise-tolerance. | Ming Zhang, Naresh R. Shanbhag |
| 2005 | ISLPED | A low-power bus design using joint repeater insertion and coding. | Srinivasa R. Sridhara, Naresh R. Shanbhag |
| 2005 | VLSID | Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. | Srinivasa R. Sridhara, Naresh R. Shanbhag |
| 2004 | DAC | A communication-theoretic design paradigm for reliable SOCs. | Naresh R. Shanbhag |
| 2004 | DAC | Coding for system-on-chip networks: a unified framework. | Srinivasa R. Sridhara, Naresh R. Shanbhag |
| 2004 | ICASSP | Switching LMS linear turbo equalization. | Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag |
| 2004 | ICCAD | A soft error rate analysis (SERA) methodology. | Ming Zhang, Naresh R. Shanbhag |
| 2004 | ICCD | Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. | Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag |
| 2004 | ISCAS | Switching methods for linear turbo equalization. | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer |
| 2004 | ISIT | Reduced complexity interpolation for soft-decoding of reed-solomon codes. | Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag |
| 2003 | GLOBECOM | Analysis of linear turbo equalizer via EXIT chart. | Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag |
| 2003 | ICCD | Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. | Ganesh Balamurugan, Naresh R. Shanbhag |
| 2003 | ISCAS | High bandwidth transimpedance amplifier design using active transmission lines. | Hyeon-Min Bae, Naresh R. Shanbhag |
| 2003 | ISCAS | Architecture-aware low-density parity-check codes. | Mohammad M. Mansour, Naresh R. Shanbhag |
| 2003 | ISCAS | Performance analysis of algorithmic noise-tolerance techniques. | Byonghyo Shim, Naresh R. Shanbhag |
| 2003 | ISLPED | A low-power VLSI architecture for turbo decoding. | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer |
| 2002 | DAC | Reliable and energy-efficient digital signal processing. | Naresh R. Shanbhag |
| 2002 | GLOBECOM | Turbo decoder architectures for low-density parity-check codes. | Mohammad M. Mansour, Naresh R. Shanbhag |
| 2002 | ICASSP | Design methodology for high-speed iterative decoder architectures. | Mohammad M. Mansour, Naresh R. Shanbhag |
| 2002 | ISCAS | Simplified current and delay models for deep submicron CMOS digital circuits. | Mohammad M. Mansour, Naresh R. Shanbhag |
| 2002 | ISLPED | Low-power VLSI decoder architectures for LDPC codes. | Mohammad M. Mansour, Naresh R. Shanbhag |
| 2001 | ISLPED | Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. | Lei Wang, Naresh R. Shanbhag |
| 2000 | ICASSP | Low-power digital filtering via soft DSP. | Rajamohana Hegde, Naresh R. Shanbhag |
| 2000 | ICCAD | Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. | Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang |
| 2000 | ISCAS | Low-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform. | Dongwon Seo, Naresh R. Shanbhag, Milton Feng |
| 2000 | ISCAS | Energy-efficiency bounds for noise-tolerant dynamic circuits. | Naresh R. Shanbhag, Lei Wang |
| 2000 | ISCAS | Architecture driven filter transformations. | Manish Sharma, Naresh R. Shanbhag |
| 2000 | ISLPED | Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). | Naresh R. Shanbhag, Krishnamurthy Soumyanath, Samuel Martin |
| 1999 | ICASSP | Low-power channel coding via dynamic reconfiguration. | Manish Goel, Naresh R. Shanbhag |
| 1999 | ISCAS | Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. | Rajamohana Hegde, Naresh R. Shanbhag |
| 1999 | ISCAS | Low-power distributed arithmetic architectures using nonuniform memory partitioning. | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
| 1999 | ISCAS | Noise-tolerant dynamic circuit design. | Lei Wang, Naresh R. Shanbhag |
| 1999 | ISLPED | Energy-efficient dynamic circuit design in the presence of crosstalk noise. | Ganesh Balamurugan, Naresh R. Shanbhag |
| 1999 | ISLPED | Energy-efficient signal processing via algorithmic noise-tolerance. | Rajamohana Hegde, Naresh R. Shanbhag |
| 1999 | MMSP | A low power data-adaptive motion estimation algorithm. | Jayanto Minocha, Naresh R. Shanbhag |
| 1999 | VLSID | Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. | Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag |
| 1998 | ICASSP | Improving the throughput of flexible-precision DSPS via algorithm transformation. | Manoj Aggarwal, Naresh R. Shanbhag, Narendra Ahuja |
| 1998 | ICASSP | Low-power reconfigurable signal processing via dynamic algorithm transformations (DAT). | Manish Goel, Naresh R. Shanbhag |
| 1998 | ICCAD | Energy-efficiency in presence of deep submicron noise. | Rajamohana Hegde, Naresh R. Shanbhag |
| 1998 | ISLPED | Decorrelating (DECOR) transformations for low-power adaptive filters. | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
| 1998 | MMSP | Efficient wireless image transmission under a total power constraint. | Swaroop Appadwedula, Manish Goel, Douglas L. Jones, Kannan Ramchandran, Naresh R. Shanbhag |
| 1998 | VLSID | Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
| 1997 | DAC | Analytical Estimation of Transition Activity From Word-Level Signal Statistics. | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
| 1997 | ICCAD | Achievable bounds on signal transition activity. | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj |
| 1997 | ISLPED | Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. | Manish Goel, Naresh R. Shanbhag |
| 1996 | ISLPED | Low-power adaptive filter architectures via strength reduction. | Manish Goel, Naresh R. Shanbhag |
| 1996 | ISLPED | Lower bounds on power dissipation for DSP algorithms. | Naresh R. Shanbhag |
| 1995 | ISCAS | Pipelined Adaptive IIR Filter Architecture. | Naresh R. Shanbhag, Gi-Hong Im |
| 1993 | ISCAS | Roundoff error analysis of the pipelined ADPCM coder. | Naresh R. Shanbhag, Keshab K. Parhi |
| 1993 | ISCAS | A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. | Naresh R. Shanbhag, Keshab K. Parhi |