Ney Laert Vilar Calazans
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
20
Venues
8
Active years
1994–2022
Best venue rank
C
Where they publish
Papers
20 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ISCAS | Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers. | Rodrigo N. Wuerdig, Marcos L. L. Sartori, Brunno A. Abreu, Sergio Bampi, Ney Laert Vilar Calazans |
| 2021 | ISCAS | Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. | Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans |
| 2020 | ISCAS | Leveraging QDI Robustness to Simplify the Design of IoT Circuits. | Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans |
| 2020 | ISCAS | Towards an Integrated Software Development Environment for Robotic Applications in MPSoCs with Support for Energy Estimations. | Paulo H. Vancin, Anderson R. P. Domingues, Marcelo Paravisi, Sergio F. Johann, Ney Laert Vilar Calazans, Alexandre M. Amory |
| 2015 | DSD | A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. | Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans |
| 2015 | VLSID | Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. | Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans |
| 2013 | DSD | LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries. | Matheus Trevisan Moreira, Carlos Henrique Menezes Oliveira, Ney Laert Vilar Calazans, Luciano Copello Ost |
| 2013 | ICCD | Voltage scaling on C-elements: A speed, power and energy efficiency analysis. | Matheus Trevisan Moreira, Ney Laert Vilar Calazans |
| 2013 | RSP | BaBaNoC: An asynchronous network-on-chip described in Balsa. | Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans |
| 2012 | RSP | A spectrum of MPSoC models for design space exploration and its use. | Carlos A. Petry, Eduardo Wchter, Guilherme M. Castilhos, Fernando Gehm Moraes, Ney Laert Vilar Calazans |
| 2011 | RSP | Arbitration and routing impact on NoC design. | Edson I. Moreno, Csar A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes |
| 2009 | ISCAS | HeMPS - a Framework for NoC-based MPSoC Generation. | Everton Carara, Roberto P. de Oliveira, Ney Laert Vilar Calazans, Fernando Gehm Moraes |
| 2008 | RSP | Integrating Abstract NoC Models within MPSoC Design. | Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya |
| 2007 | ISCAS | Evaluation of Algorithms for Low Energy Mapping onto NoCs. | Csar A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes |
| 2005 | DATE | Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. | Csar A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel |
| 2005 | ISCAS | Energy and latency evaluation of NoC topologies. | Mrcio Eduardo Kreutz, Csar A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans |
| 2005 | RSP | Models for Embedded Application Mapping onto NoCs: Timing Analysis. | Csar A. M. Marcon, Mrcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans |
| 2004 | FPL | FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. | Leandro Mller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brio, Ewerson Carvalho, Daniel Camozzato |
| 2003 | DATE | Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. | Fernando Gehm Moraes, Daniel Mesquita, Jos Carlos S. Palma, Leandro Mller, Ney Laert Vilar Calazans |
| 1994 | ICCAD | Boolean constrained encoding: a new formulation and a case study. | Ney Laert Vilar Calazans |