Nobuyoshi Nomizu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
1980–1991
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1991 | DAC | Timing Optimization on Mapped Circuits. | Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh |
| 1990 | ICCAD | A Framework Environment for Logic Design Support System. | Kaname Kuroki, Nobuyoshi Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi |
| 1990 | ICCD | HAL III: function level hardware logic simulation. | Shigeru Takasaki, Nobuyoshi Nomizu, Yoshihiro Hirabayashi, Hiroshi Ishikura, Masahiro Kurashita, Nobuhiko Koike, Toshiyuki Nakata |
| 1986 | DAC | HAL II: a mixed level hardware logic simulation system. | Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Hiroshi Ishikura, Nobuhiko Koike |
| 1984 | ITC | Logic Design Verification Using Automated Test Generation. | Tohru Sasaki, Shunichi Kato, Nobuyoshi Nomizu, Hidetoshi Tanaka |
| 1980 | DAC | MIXS: A mixed level simulator for large digital system logic verification. | Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu |