| 2023 | CloudCom | A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. | Qiangfeng Shen, Paul Chow |
| 2023 | FPL | Partitioning Large-Scale, Multi-FPGA Applications for the Data Center. | Mohammadmahdi Mazraeli, Yu Gao, Paul Chow |
| 2021 | FCCM | Pharos: a Performance Monitor for Multi-FPGA Systems. | Arzhang Rafii, Paul Chow, Welson Sun |
| 2021 | FCCM | FFIVE: An FPGA Framework for Interactive VNF Environments. | Juan Camilo Vega, Mohammad Ewais, Alberto Leon-Garcia, Paul Chow |
| 2021 | FPGA | Interactive Debugging at IP Block Interfaces in FPGAs. | Marco Antonio Merlini, Isamu Poy, Paul Chow |
| 2021 | FPGA | Exploring PGAS Communication for Heterogeneous Clusters with FPGAs. | Varun Sharma, Paul Chow |
| 2021 | FPGA | RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication. | Qianfeng Clark Shen, Jun Zheng, Paul Chow |
| 2021 | FPL | Pharos: a Multi-FPGA Performance Monitor. | Arzhang Rafii, Welson Sun, Paul Chow |
| 2020 | FCCM | Hierarchical Modelling of Generators in Design-Space Exploration. | Charles Lo, Paul Chow |
| 2020 | FCCM | AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters. | Naif Tarafdar, Giuseppe Di Guglielmo, Philip C. Harris, Jeffrey D. Krupa, Vladimir Loncar, Dylan S. Rankin, Nhan Tran, Zhenbin Wu, Qianfeng Shen, Paul Chow |
| 2020 | FCCM | FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark. | Juan Camilo Vega, Marco Antonio Merlini, Paul Chow |
| 2020 | FCCM | SHIP: Storage for Hybrid Interconnected Processors. | Juan Camilo Vega, Qianfeng Clark Shen, Paul Chow |
| 2019 | FCCM | Sonar: Writing Testbenches through Python. | Varun Sharma, Naif Tarafdar, Paul Chow |
| 2019 | FPGA | A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center. | Nariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, Paul Chow |
| 2019 | FPGA | The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs. | Daniel Rozhko, Paul Chow |
| 2019 | IM | Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network. | Juan Camilo Vega, Qianfeng Shen, Alberto Leon-Garcia, Paul Chow |
| 2018 | FCCM | A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media. | Abdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow |
| 2018 | FPL | Multi-fidelity Optimization for High-Level Synthesis Directives. | Charles Lo, Paul Chow |
| 2017 | APNOMS | Enabling network function virtualization over heterogeneous resources. | Thomas Lin, Naif Tarafdar, Byungchul Park, Paul Chow, Alberto Leon-Garcia |
| 2017 | ASPLOS | Building the Reconfigurable Cloud Ecosystem. | Paul Chow |
| 2017 | FPGA | Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules. | Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen |
| 2017 | FPGA | Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center. | Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow |
| 2017 | FPL | Heterogeneous virtualized network function framework for the data center. | Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow |
| 2016 | FCCM | Accelerating Apache Spark Big Data Analysis with FPGAs. | Ehsan Ghasemi, Paul Chow |
| 2016 | FPGA | A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only). | Ehsan Ghasemi, Paul Chow |
| 2016 | FPL | Model-based optimization of High Level Synthesis directives. | Charles Lo, Paul Chow |
| 2016 | UIC | Accelerating Apache Spark Big Data Analysis with FPGAs. | Ehsan Ghasemi, Paul Chow |
| 2015 | FPGA | Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware. | Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow |
| 2014 | FCCM | FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack. | Stuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow |
| 2014 | FPGA | MPack: global memory optimization for stream applications in high-level synthesis. | Jasmina Vasiljevic, Paul Chow |
| 2014 | FPL | Using an OpenCL framework to evaluate interconnect implementations on FPGAs. | Vincent Mirian, Paul Chow |
| 2014 | FPL | Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use. | Jasmina Vasiljevic, Paul Chow |
| 2014 | TridentCom | Virtualized Reconfigurable Hardware Resources in the SAVI Testbed. | Stuart Byma, Hadi Bannazadeh, Alberto Leon-Garcia, J. Gregory Steffan, Paul Chow |
| 2013 | FPGA | A remote memory access infrastructure for global address space programming models in FPGAs. | Ruediger Willenberg, Paul Chow |
| 2013 | FPL | NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract. | Stuart Byma, J. Gregory Steffan, Paul Chow |
| 2013 | FPL | Simulation-based HW/SW co-debugging for field-programmable systems-on-chip. | Ruediger Willenberg, Paul Chow |
| 2013 | FPL | SimXMD: Simulation-based HW/SW co-debugging. | Ruediger Willenberg, Paul Chow |
| 2012 | FPGA | OpenCL memory infrastructure for FPGAs (abstract only). | S. Alexander Chin, Paul Chow |
| 2012 | FPGA | FCache: a system for cache coherent processing on FPGAs. | Vincent Mirian, Paul Chow |
| 2012 | FPL | K-means implementation on FPGA for high-dimensional data using triangle inequality. | Zhongduo Lin, Charles Lo, Paul Chow |
| 2011 | FPGA | Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. | Charles Lo, Paul Chow |
| 2011 | FPL | Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. | Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang |
| 2011 | FPL | Hardware Support for Broadcast and Reduce in MPSoC. | Yuanxi Peng, Manuel Saldaa, Paul Chow |
| 2010 | FCCM | Integrating High-Level Synthesis into MPI. | Andrew W. H. House, Manuel Saldaa, Paul Chow |
| 2010 | FPGA | Acceleration of an analytical approach to collateralized debt obligation pricing. | Dharmendra P. Gupta, Paul Chow |
| 2010 | TridentCom | Virtualized Application Networking Infrastructure. | Hadi Bannazadeh, Alberto Leon-Garcia, Keith Redmond, Gordon Tam, Arbab Khan, Mingliang Ma, Saleh Dani, Paul Chow |
| 2009 | FCCM | FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. | Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose |
| 2009 | FPGA | A high-performance FPGA architecture for restricted boltzmann machines. | Daniel Le Ly, Paul Chow |
| 2009 | FPL | A multi-FPGA architecture for stochastic Restricted Boltzmann Machines. | Daniel Le Ly, Paul Chow |
| 2008 | FCCM | Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems. | Andrew W. H. House, Paul Chow |
| 2008 | FPL | FPGA acceleration of Monte-Carlo based credit derivative pricing. | Alexander Kaganov, Paul Chow, Asif Lakhany |
| 2008 | SC | MPI as an abstraction for software-hardware interaction for HPRCs. | Manuel Saldaa, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Henry Styles, Andrew Putnam, Ralph Wittig, Paul Chow |
| 2007 | FPGA | Integrating FPGAs in high-performance computing: introduction. | Paul Chow, Mike Hutton |
| 2007 | ICS | Optimization of data prefetch helper threads with path-expression based statistical modeling. | Tor M. Aamodt, Paul Chow |
| 2006 | FCCM | A Scalable FPGA-based Multiprocessor. | Arun Patel, Christopher A. Madill, Manuel Saldaa, Chris Comis, Rgis Poms, Paul Chow |
| 2006 | FPGA | The routability of multiprocessor network topologies in FPGAs. | Manuel Saldaa, Lesley Shannon, Paul Chow |
| 2006 | FPL | TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. | Manuel Saldaa, Paul Chow |
| 2006 | FPL | A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. | Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaa, Paul Chow |
| 2005 | FCCM | Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. | Lesley Shannon, Paul Chow |
| 2005 | FPL | Leveraging Reconfigurability in the Design Process. | Lesley Shannon, Paul Chow |
| 2004 | FCCM | Reconfigurable Molecular Dynamics Simulator. | Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow |
| 2004 | FPGA | FPGA-based supercomputing: an implementation for molecular dynamics. | Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow |
| 2004 | FPGA | Using reconfigurability to achieve real-time profiling for hardware/software codesign. | Lesley Shannon, Paul Chow |
| 2004 | HPCA | Hardware Support for Prescient Instruction Prefetch. | Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen |
| 2003 | FCCM | Standardizing the Performance Assessment of Reconfigurable Processor Architectures. | Lesley Shannon, Paul Chow |
| 2003 | SIGMETRICS | A framework for modeling and optimization of prescient instruction prefetch. | Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio Gonzlez, Per Hammarlund, Hong Wang, John Paul Shen |
| 2001 | FPGA | The effect of reconfigurable units in superscalar processors. | Jorge E. Carrillo, Paul Chow |
| 2000 | CASES | Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. | Tor M. Aamodt, Paul Chow |
| 1999 | CHES | DES Cracking on the Transmogrifier 2a. | Ivan Hamer, Paul Chow |
| 1999 | FPGA | Memory Interfacing and Instruction Specification for Reconfigurable Processors. | Jeffrey A. Jacob, Paul Chow |
| 1997 | FPGA | The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. | David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow |
| 1997 | ISCA | Memory-System Design Considerations for Dynamically-Scheduled Processors. | Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic |
| 1997 | MICRO | The Multicluster Architecture: Reducing Cycle Time Through Partitioning. | Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic |
| 1996 | ASPLOS | Exploiting Dual Data-Memory Banks in Digital Signal Processors. | Mazen A. R. Saghir, Paul Chow, Corinna G. Lee |
| 1996 | FCCM | OneChip: an FPGA processor with reconfigurable logic. | Ralph Wittig, Paul Chow |
| 1996 | FCCM | RACER: a reconfigurable constraint-length 14 Viterbi decoder. | David Yeh, Gennady Feygin, Paul Chow |
| 1996 | HPCA | Register File Design Considerations in Dynamically Scheduled Processors. | Keith I. Farkas, Norman P. Jouppi, Paul Chow |
| 1995 | FPGA | A Field-Programmable Mixed-Analog-Digital Array. | Paul Chow, P. Glenn Gulak |
| 1995 | HPCA | How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? | Keith I. Farkas, Norman P. Jouppi, Paul Chow |
| 1994 | DCC | Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. | Gennady Feygin, P. Glenn Gulak, Paul Chow |
| 1994 | ICASSP | Application-driven design of DSP architectures and compilers. | Mazen A. R. Saghir, Paul Chow, Corinna G. Lee |
| 1993 | DCC | Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. | Gennady Feygin, P. Glenn Gulak, Paul Chow |
| 1993 | ISCAS | A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. | Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton |
| 1991 | ICASSP | Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. | Gennady Feygin, Patrick Glenn Gulak, Paul Chow |
| 1991 | ICASSP | A streamlined DSP microprocessor architecture. | Michael Takefman, Paul Chow |
| 1987 | ISCA | Architectural Tradeoffs in the Design of MIPS-X. | Paul Chow, Mark Horowitz |