| 2025 | DDECS | Controllability-Based Circuit Similarity Estimation. | Michal Zcek, Petr Fiser |
| 2024 | DDECS | A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks. | Jan Schmidt, Petr Fiser, Miroslav Skrbek |
| 2024 | DDECS | Adaptive Input Normalization for Quantized Neural Networks. | Jan Schmidt, Petr Fiser, Miroslav Skrbek |
| 2024 | DSD | Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation. | Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das |
| 2023 | DDECS | Reducing Output Response Aliasing Using Boolean Optimization Techniques. | Robert Hlle, Petr Fiser, Jan Schmidt |
| 2022 | DDECS | A Design Space Exploration Framework for Memristor-Based Crossbar Architecture. | Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola |
| 2021 | DDECS | Emerging Technologies: Challenges and Opportunities for Logic Synthesis. | Alberto Bosio, Mayeul Cantan, Cdric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola |
| 2021 | VLSID | Minimization of Switching Activity of Graphene Based Circuits. | Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das |
| 2020 | DDECS | Standard Cell Tuning Enables Data-Independent Static Power Consumption. | Jan Belohoubek, Petr Fiser, Jan Schmidt |
| 2020 | DSD | Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing. | Jaroslav Boreck, Robert Hlle, Petr Fiser |
| 2019 | DDECS | Using Voters May Lead to Secret Leakage. | Jan Belohoubek, Petr Fiser, Jan Schmidt |
| 2019 | DSD | CMOS Illumination Discloses Processed Data. | Jan Belohoubek, Petr Fiser, Jan Schmidt |
| 2018 | DDECS | Synthesis of Finite State Machines on Memristor Crossbars. | Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio |
| 2017 | DDECS | Are XORs in logic synthesis really necessary? | Ivo Hlecek, Petr Fiser, Jan Schmidt |
| 2017 | DSD | SAT-Based Generation of Optimum Function Implementations with XOR Gates. | Petr Fiser, Ivo Hlecek, Jan Schmidt |
| 2017 | DSD | SAT-Based ATPG for Zero-Aliasing Compaction. | Robert Hlle, Petr Fiser, Jan Schmidt |
| 2016 | DDECS | A rule-based approach for minimizing power dissipation of digital circuits. | Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das |
| 2016 | DDECS | A new user-friendly ATPG platform for digital circuits. | Marek Lipovsk, Jn Svarc, Elena Gramatov, Petr Fiser |
| 2016 | DDECS | A new method for path criticality calculation. | Rbert Tamsi, Miroslav Siebert, Elena Gramatov, Petr Fiser |
| 2016 | DSD | Error Correction Method Based on the Short-Duration Offline Test. | Jan Belohoubek, Petr Fiser, Jan Schmidt |
| 2015 | DSD | Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy. | Jan Belohoubek, Petr Fiser, Jan Schmidt |
| 2014 | DDECS | Sources of bias in EDA tools and its influence. | Petr Fiser, Jan Schmidt, Jiri Balcarek |
| 2014 | DSD | PBO-Based Test Compression. | Jiri Balcarek, Petr Fiser, Jan Schmidt |
| 2014 | DSD | On Robustness of EDA Tools. | Jan Schmidt, Petr Fiser, Jiri Balcarek |
| 2013 | DSD | Simulation and SAT Based ATPG for Compressed Test Generation. | Jiri Balcarek, Petr Fiser, Jan Schmidt |
| 2012 | DDECS | Improving the iterative power of resynthesis. | Petr Fiser, Jan Schmidt |
| 2012 | DSD | The Influence of Implementation Technology on Dependability Parameters. | Jan Schmidt, Petr Fiser, Jiri Balcarek |
| 2011 | DSD | Techniques for SAT-Based Constrained Test Pattern Generation. | Jiri Balcarek, Petr Fiser, Jan Schmidt |
| 2010 | DDECS | On logic synthesis of conventionally hard to synthesize circuits using genetic programming. | Petr Fiser, Jan Schmidt, Zdenek Vascek, Luks Sekanina |
| 2010 | DSD | Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. | Jiri Balcarek, Petr Fiser, Jan Schmidt |
| 2010 | DSD | Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. | Igor Lemberski, Petr Fiser |
| 2009 | DDECS | Asynchronous two-level logic of reduced cost. | Igor Lemberski, Petr Fiser |
| 2009 | DSD | A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms. | Petr Fiser, David Toman |
| 2009 | DSD | The Case for a Balanced Decomposition Process. | Jan Schmidt, Petr Fiser |
| 2008 | DDECS | Fast Boolean Minimizer for Completely Specified Functions. | Petr Fiser, Pemysl Ruck, Irena Vanov |
| 2008 | DSD | An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. | Petr Fiser, Pavel Kubalk, Hana Kubtov |
| 2007 | DSD | Pseudo-Random Pattern Generator Design for Column-Matching BIST. | Petr Fiser |
| 2006 | DDECS | Multiple-Vector Column-Matching BIST Design Method. | Petr Fiser, Hana Kubtov |
| 2006 | DSD | Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications. | Petr Fiser, Hana Kubtov |
| 2006 | IOLTS | Fault Tolerant System Design Method Based on Self-Checking Circuits. | Pavel Kubalk, Petr Fiser, Hana Kubtov |
| 2004 | DSD | Boolean Minimizer FC-Min: Coverage Finding Process. | Petr Fiser, Hana Kubtov |
| 2004 | IOLTS | Survey of the Algorithms in the Column-Matching BIST Method. | Petr Fiser, Hana Kubtov |
| 2003 | DSD | FC-Min: A Fast Multi-Output Boolean Minimizer. | Petr Fiser, Jan Hlavicka, Hana Kubtov |
| 2001 | DSD | On the Use of Mutations in Boolean Minimization. | Petr Fiser, Jan Hlavicka |
| 2001 | ICCAD | BOOM - A Heuristic Boolean Minimizer. | Jan Hlavicka, Petr Fiser |