| 2016 | FMCAD | A paradigm shift in verification methodology. | Pranav Ashar |
| 2013 | FMCAD | Static verification based signoff - A key enabler for managing verification complexity in the modern soc. | Pranav Ashar |
| 2005 | CAV | F-Soft: Software Verification Platform. | Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar |
| 2005 | DAC | Beyond safety: customized SAT-based model checking. | Malay K. Ganai, Aarti Gupta, Pranav Ashar |
| 2005 | DATE | Verification of Embedded Memory Systems using Efficient Memory Modeling. | Malay K. Ganai, Aarti Gupta, Pranav Ashar |
| 2005 | VLSID | Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. | Aarti Gupta, Malay K. Ganai, Pranav Ashar |
| 2005 | TACAS | Untitled record | Malay K. Ganai, Aarti Gupta, Pranav Ashar |
| 2004 | CAV | Efficient Modeling of Embedded Memories in Bounded Model Checking. | Malay K. Ganai, Aarti Gupta, Pranav Ashar |
| 2004 | ICCAD | Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. | Malay K. Ganai, Aarti Gupta, Pranav Ashar |
| 2004 | ISoLA | Efficient SAT-based Bounded Model Checking for Software Verification. | Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang |
| 2003 | CAV | Abstraction and BDDs Complement SAT-Based BMC in DiVer. | Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar |
| 2003 | DAC | Learning from BDDs in SAT-based bounded model checking. | Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar |
| 2003 | ICCAD | Iterative Abstraction using SAT-based BMC with Proof Analysis. | Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar |
| 2002 | DAC | A fast, inexpensive and scalable hardware acceleration technique for functional simulation. | Srihari Cadambi, Chandra Mulpuri, Pranav Ashar |
| 2002 | DAC | Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. | Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik |
| 2002 | VLSID | Property-Specific Testbench Generation for Guided Simulation. | Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi |
| 2001 | DAC | Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. | Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar |
| 2001 | DATE | Property-specific witness graph generation for guided simulation. | Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar |
| 2001 | ICCAD | Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. | Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik |
| 2000 | FMCAD | SAT-Based Image Computation with Application in Reachability Analysis. | Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta |
| 2000 | VLSID | Fast Error Diagnosis for Combinational Verification. | Aarti Gupta, Pranav Ashar |
| 2000 | VLSID | Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. | Yang Xia, Pranav Ashar |
| 1999 | DAC | Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. | Farzan Fallah, Pranav Ashar, Srinivas Devadas |
| 1999 | FCCM | An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. | Zhen Luo, Margaret Martonosi, Pranav Ashar |
| 1999 | ICCD | Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. | Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya |
| 1998 | DAC | Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. | Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi |
| 1998 | FCCM | Accelerating Boolean Satisfiability with Configurable Hardware. | Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik |
| 1998 | FPL | Solving Boolean Satisfiability with Dynamic Hardware Configurations. | Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik |
| 1998 | ICCAD | Verification of RTL generated from scheduled behavior in a high-level synthesis flow. | Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama |
| 1998 | VLSID | Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. | Aarti Gupta, Pranav Ashar |
| 1997 | DAC | Toward Formalizing a Validation Methodology Using Simulation Coverage. | Aarti Gupta, Sharad Malik, Pranav Ashar |
| 1996 | DAC | Scheduling Techniques to Enable Power Management. | Jos Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar |
| 1996 | ICCAD | Using complete-1-distinguishability for FSM equivalence checking. | Pranav Ashar, Aarti Gupta, Sharad Malik |
| 1995 | ICCAD | Fast functional simulation using branching programs. | Pranav Ashar, Sharad Malik |
| 1995 | ISLPED | Guarded evaluation: pushing power management to logic synthesis/design. | Vivek Tiwari, Sharad Malik, Pranav Ashar |
| 1995 | VLSID | Test generation for cyclic combinational circuits. | Anand Raghunathan, Pranav Ashar, Sharad Malik |
| 1994 | DAC | Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. | Pranav Ashar, Sharad Malik |
| 1994 | ICCAD | Efficient breadth-first manipulation of binary decision diagrams. | Pranav Ashar, Matthew Cheong |
| 1993 | DAC | Technology Mapping for Lower Power. | Vivek Tiwari, Pranav Ashar, Sharad Malik |
| 1992 | ICCAD | Exploiting multi-cycle false paths in the performance optimization of sequential circuits. | Pranav Ashar, Sujit Dey, Sharad Malik |
| 1991 | ICCD | Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. | Pranav Ashar, Abhijit Ghosh, Srinivas Devadas |
| 1991 | ITC | Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. | Pranav Ashar, Srinivas Devadas, Kurt Keutzer |
| 1990 | DAC | A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. | Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| 1990 | ICCAD | Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. | Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| 1990 | ICCD | Testability driven synthesis of interacting finite state machines. | Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| 1989 | ICCAD | Optimum and heuristic algorithms for finite state machine decomposition and partitioning. | Pranav Ashar, Srinivas Devadas, A. Richard Newton |