Rafael Trapani Possignolo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
8
Active years
2012–2020
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | ISPASS | LiveSim: A Fast Hot Reload Simulator for HDLs. | Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau |
| 2019 | DAC | SMatch: Structural Matching for Fast Resynthesis in FPGAs. | Rafael Trapani Possignolo, Jose Renau |
| 2019 | MICRO | EMI Architectural Model and Core Hopping. | Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau |
| 2017 | DAC | LiveSynth: Towards an Interactive Synthesis Flow. | Rafael Trapani Possignolo, Jose Renau |
| 2017 | ISCAS | Level shifter design for voltage stacking. | Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau |
| 2017 | MEMOCODE | Liam: an actor based programming model for HDLs. | Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau |
| 2016 | FPL | Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. | Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das |
| 2016 | ICCD | Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. | Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau |
| 2016 | ISCAS | SRAM voltage stacking. | Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau |
| 2012 | TrustCom | A Quantum-classical Hybrid Architecture for Security Algorithms Acceleration. | Rafael Trapani Possignolo, Cntia B. Margi |