Rahul M. Rao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
18
Venues
8
Active years
1978–2024
Best venue rank
A*
Where they publish
Papers
18 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | DATE | Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster Balancing. | George Antony, Gireesh Kumar K. M, Naiju Karim Abdul, Rahul M. Rao |
| 2021 | ISCA | Energy Efficiency Boost in the AI-Infused POWER10 Processor. | Brian W. Thompto, Dung Q. Nguyen, Jos E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Mller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose |
| 2018 | VLSID | Impact of Device Aging on Early Mode Failures in Pulsed Latches. | Ankur Shukla, Rahul M. Rao, James D. Warnock |
| 2018 | VLSID | A High Performance Gated Voltage Level Translator with Integrated Multiplexer. | Dharshak B. S., Rahul M. Rao |
| 2016 | ISLPED | FVCAG: A framework for formal verification driven power modeling and verification. | Arun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla |
| 2013 | ETS | Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. | Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif |
| 2013 | ICCAD | Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. | Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez |
| 2009 | ISCAS | A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. | Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang |
| 2009 | ISLPED | A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. | Amlan Ghosh, Rahul M. Rao, Richard B. Brown |
| 2008 | ISCAS | Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang |
| 2008 | VLSID | On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. | Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown |
| 2005 | ISCAS | Power-aware global signaling strategies. | Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif |
| 2004 | ISLPED | Approaches to run-time and standby mode leakage reduction in global buses. | Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif |
| 2004 | VLSID | Analysis and Optimization of Enhanced MTCMOS Scheme. | Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown |
| 2003 | ICCAD | A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. | Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown |
| 2003 | ISLPED | Leakage and leakage sensitivity computation for combinational circuits. | Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns |
| 2003 | ISLPED | Efficient techniques for gate leakage estimation. | Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown |
| 1978 | ICASSP | Frequency estimation by linear prediction. | Leland B. Jackson, Donald W. Tufts, Frank K. Soong, Rahul M. Rao |