Rajesh Velegalati
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
2009–2024
Best venue rank
B
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | FDTC | Improving CPU Fault Injection Simulations: Insights from RTL to Instruction-Level Models. | Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Dennis Vermoen Riscure |
| 2023 | VTS | Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. | Sohrab Aftabjahani, Mark Tehranipoor, Farimah Farahmandi, Bulbul Ahmed, Ryan Kastner, Francesco Restuccia, Andres Meza, Kaki Ryan, Nicole Fern, Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Cynthia Sturton, Calvin Deutschbein |
| 2013 | DSD | Glitch Detection in Hardware Implementations on FPGAs Using Delay Based Sampling Techniques. | Rajesh Velegalati, Kinjal Shah, Jens-Peter Kaps |
| 2011 | FPL | Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs. | Rajesh Velegalati, Jens-Peter Kaps |
| 2010 | FCCM | DPA Resistant AES on FPGA Using Partial DDL. | Jens-Peter Kaps, Rajesh Velegalati |
| 2009 | FPL | DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs. | Rajesh Velegalati, Jens-Peter Kaps |