| 2025 | DAC | Invited: EDA for Heterogeneous Integration. | Emad Haque, Pragnya Sudershan Nalla, Chetal Choppali Sudarshan, Divya Yogi, Hangyu Zhang, Chaitali Chakrabarti, Vidya A. Chhabria, Ramesh Harjani, Jeff Zhang, Sachin S. Sapatnekar |
| 2025 | DATE | Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. | Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar |
| 2025 | ICCAD | Optimal Selection and Placement of Voltage Regulators in 2.5D Heterogeneously Integrated Systems. | Hangyu Zhang, Divya Yogi, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | ASPDAC | Reinforcing the Connection between Analog Design and EDA (Invited Paper). | Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | ASPDAC | Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. | Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar |
| 2024 | ICCAD | Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power Amplifiers. | Nibedita Karmokar, Sai-Wang Tam, Thanh Viet Dinh, Vidya A. Chhabria, Ramesh Harjani, Sachin S. Sapatnekar |
| 2023 | DATE | AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. | Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun |
| 2023 | DATE | Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. | Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar |
| 2022 | ASPDAC | Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. | Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar |
| 2022 | DATE | A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. | Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar |
| 2022 | DATE | Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. | Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar |
| 2022 | DATE | Are Analytical Techniques Worthwhile for Analog IC Placement? | Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu |
| 2021 | ASPDAC | Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. | Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar |
| 2021 | DATE | Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. | Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar |
| 2021 | ICCAD | From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. | Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen |
| 2021 | ICCAD | Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. | Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar |
| 2020 | DATE | GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. | Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar |
| 2020 | ICCAD | The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). | Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar |
| 2020 | ICCAD | A general approach for identifying hierarchical symmetry constraints for analog circuit layout. | Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar |
| 2020 | ICCAD | A Customized Graph Neural Network Model for Guiding Analog IC Placement. | Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu |
| 2019 | DAC | ALIGN: Open-Source Analog Layout Automation from the Ground Up. | Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar |
| 2010 | ISCAS | Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%). | Bodhisatwa Sadhu, Ramesh Harjani |
| 2007 | ISCAS | High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator. | Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani |
| 2005 | ISCAS | Process tolerant design of N-tone Sigma-Delta converters. | Shubha Bommalingaiahnapallya, Ramesh Harjani |
| 2005 | ISCAS | Power optimized LC VCO and mixer co-design. | Byunghoo Jung, Shubha Bommalingaiahnapallya, Ramesh Harjani |
| 2005 | ISCAS | Pulse generator design for UWB IR communication systems. | Byunghoo Jung, Yi-Hung Tseng, Jackson Harvey, Ramesh Harjani |
| 2005 | VLSID | High-Speed Interconnect Technology: On-Chip and Off-Chip. | Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani |
| 2004 | ISCAS | Low power implementation of an n-tone Sigma Delta converter. | Shubha Bommalingaiahnapallya, Ramesh Harjani |
| 2004 | ISCAS | A wide tuning range VCO using capacitive source degeneration. | Byunghoo Jung, Ramesh Harjani |
| 2004 | VLSID | Analog/RF Physical Layer Issues For UWB Systems. | Ramesh Harjani, Jackson Harvey, Robert Sainati |
| 2003 | ISCAS | A novel noise optimization design technique for radio frequency low noise amplifiers. | Byunghoo Jung, Anand Gopinath, Ramesh Harjani |
| 2003 | ISCAS | Novel integratable notch filter implementation for 100 dB image rejection. | Deepa S. Parthasarathy, Ramesh Harjani |
| 2001 | ISCAS | Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages. | Ron Balczewski, Ramesh Harjani |
| 2001 | ISCAS | Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter. | Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota |
| 2001 | ISCAS | Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection. | Jackson Harvey, Ramesh Harjani |
| 2001 | ISCAS | Power optimization of CMOS LC VCOs. | Ming-Ta Hsieh, Jackson Harvey, Ramesh Harjani |
| 2001 | ISCAS | An ISM band CMOS integrated transceiver design for wireless telemetry system. | Jonghae Kim, Ramesh Harjani |
| 2001 | VLSID | Tutorial: CMOS Analog Circuits for Wireless Communications. | Ramesh Harjani, Jackson Harvey |
| 2001 | VLSID | An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage. | Jackson Harvey, Ramesh Harjani |
| 2000 | ISCAS | Comparison and analysis of phase noise in ring oscillators. | Liang Dai, Ramesh Harjani |
| 2000 | ISCAS | A high speed differential to single-ended amplifier for instrumentation applications. | Doug Dean, Ramesh Harjani |
| 2000 | ISCAS | A universal analytic charge injection model. | Yongwang Ding, Ramesh Harjani |
| 2000 | ISCAS | An IF stage design for an ASK-based wireless telemetry system. | Ramesh Harjani, Oyvind Birkenes, Jonghae Kim |
| 2000 | ISLPED | Analysis and design of low-phase-noise ring oscillators. | Liang Dai, Ramesh Harjani |
| 2000 | VLSID | Analog Circuits for Wireless Communications. | Ramesh Harjani |
| 1999 | DAC | Digital Aetection of Analog Parametric Faults in SC Filters. | Ramesh Harjani, Bapiraju Vinnakota |
| 1999 | ISCAS | A telemetry and interface circuit for piezoelectric sensors. | Kavita Nair, Ramesh Harjani |
| 1999 | VLSID | Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid. | Kavita Nair, Ramesh Harjani |
| 1997 | VLSID | T5: Low-Power Design. | Kaushik Roy, Rabindra K. Roy, Ramesh Harjani, K. S. Murthy |
| 1997 | VLSID | Pseudoduplication - An ACOB Technique for Single-Ended Circuits. | Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi |
| 1996 | VLSID | Mixed-Signal Design for Test. | Bapiraju Vinnakota, Ramesh Harjani |
| 1995 | DAC | System-Level Design for Test of Fully Differential Analog Circuits. | Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman |
| 1995 | ISCAS | Dynamic Amplifiers: Settling, Slewing and Power Issues. | Feng Wang, Ramesh Harjani |
| 1994 | ICCAD | Macromodeling of analog circuits for hierarchical circuit design. | Jianfeng Shao, Ramesh Harjani |
| 1994 | ISCAS | A 6-Bit 50MHz Current-Subtracting Two Step Flash Converter. | Andrew Cable, Ramesh Harjani |
| 1994 | VLSID | The Design of Analog Self-Checking Circuits. | Bapiraju Vinnakota, Ramesh Harjani |
| 1994 | VTS | Analog circuit observer blocks. | Ramesh Harjani, Bapiraju Vinnakota |
| 1993 | ICASSP | Acoustic feedback cancellation in hearing aids. | Rongtai Wang, Ramesh Harjani |
| 1993 | ISCAS | A Dual Frequency Range Integrated Circuit Accelerometer Using Capacitive and Piezoelectric Sensing Techniques. | Brian A. Blow, Ramesh Harjani, Dennis L. Polla, Takashi Tamagawa |
| 1993 | ISCAS | Suppression of acoustic oscillations in hearing aids using minimum phase techniques. | Rongtai Wang, Ramesh Harjani |
| 1988 | ICCAD | Analog circuit synthesis for performance in OASYS. | Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley |
| 1988 | ICCD | Analog circuit synthesis and exploration in OASYS. | Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley |
| 1987 | DAC | A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. | Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley |