Rei-Fu Huang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
5
Active years
2002–2015
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | ITC | Testing methods for quaternary content addressable memory using charge-sharing sensing scheme. | Hao-Yu Yang, Rei-Fu Huang, Chin-Lung Su, Kuan-Hong Lin, Hang-Kaung Shu, Chi-Wei Peng, Mango Chia-Tso Chao |
| 2014 | VTS | Testing methods for a write-assist disturbance-free dual-port SRAM. | Hao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango Chia-Tso Chao, Rei-Fu Huang |
| 2012 | DAC | Alternate hammering test for application-specific DRAMs and an industrial case study. | Rei-Fu Huang, Hao-Yu Yang, Mango Chia-Tso Chao, Shih-Chin Lin |
| 2010 | ITC | Fault models and test methods for subthreshold SRAMs. | Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang |
| 2009 | DAC | Fault models for embedded-DRAM macros. | Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin |
| 2008 | ITC | Testing Methodology of Embedded DRAMs. | Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen |
| 2004 | ASPDAC | SRAM delay fault modeling and test algorithm development. | Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu |
| 2004 | ITC | MRAM Defect Analysis and Fault Modeli. | Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu |
| 2003 | ITC | A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. | Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow |
| 2002 | IOLTS | A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |