Richard M. Chou
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1994–2001
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2001 | VTS | Testable Sequential Circuit Design: A Partition and Resynthesis Approach. | Richard M. Chou, Kewal K. Saluja |
| 1997 | VLSID | Sequential Circuit Testing: From DFT to SFT. | Richard M. Chou, Kewal K. Saluja |
| 1994 | VLSID | Power Constraint Scheduling of Tests. | Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal |