| 2026 | ETS | Special Session: Hardware Security at the Circuit and Layout Levels. | Sajjad Parvin, Carl Riehm, Nan Du, Ralf Brederlow, Frank Sill Torres, Rolf Drechsler |
| 2026 | VLSID | DIVIAC: Library of Input Data Aware Approximate Dividers with Partial Exact Minimization. | Chandan Kumar Jha, Sallar Ahmadi-Pour, Sajjad Parvin, Rolf Drechsler |
| 2025 | VLSID | True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET. | Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler |
| 2024 | DATE | Hidden Cost of Circuit Design with RFETs. | Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler |
| 2023 | ASPDAC | Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. | Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler |
| 2023 | DATE | FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. | Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler |
| 2022 | ASPDAC | Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. | Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler |
| 2020 | ISCAS | Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks. | Levent Aksoy, Sajjad Parvin, Mohammadreza Esmali Nojehdeh, Mustafa Altun |
| 2019 | IOLTS | Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates. | Sajjad Parvin, Mustafa Altun |