| 2020 | DATE | Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. | Valentin Gherman, Samuel Evain, Bastien Giraud |
| 2014 | ETS | Shadow-scan design with low latency overhead and in-situ slack-time monitoring. | Sbastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman |
| 2014 | IOLTS | Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. | Sbastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman |
| 2013 | DATE | Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. | Sbastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman |
| 2013 | ETS | Error-correction schemes with erasure information for fast memories. | Samuel Evain, Valentin Gherman |
| 2012 | ETS | Memory reliability improvements based on maximized error-correcting codes. | Valentin Gherman, Samuel Evain, Yannick Bonhomme |
| 2011 | DATE | Error prediction based on concurrent self-test and reduced slack time. | Valentin Gherman, J. Massas, Samuel Evain, Stphane Chevobbe, Yannick Bonhomme |
| 2011 | IOLTS | Generalized parity-check matrices for SEC-DED codes with fixed parity. | Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme |
| 2011 | VTS | Programmable extended SEC-DED codes for memory errors. | Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme |
| 2010 | IOLTS | Programmable restricted SEC codes to mask permanent faults in semiconductor memories. | Samuel Evain, Yannick Bonhomme, Valentin Gherman |
| 2009 | DATE | System-level hardware-based protection of memories against soft-errors. | Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme |