| 2024 | MICRO | UFC: A Unified Accelerator for Fully Homomorphic Encryption. | Minxuan Zhou, Yujin Nam, Xuan Wang, Youhak Lee, Chris Wilkerson, Raghavan Kumar, Sachin Taneja, Sanu Mathew, Rosario Cammarota, Tajana Rosing |
| 2020 | DAC | INVITED: A 0.26% BER, Machine-Learning Resistant 10 | Vikram B. Suresh, Raghavan Kumar, Sanu Mathew |
| 2019 | ARITH | Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators. | Himanshu Kaul, Mark A. Anders, Sanu Mathew, Seongjong Kim, Ram Krishnamurthy |
| 2018 | DATE | Ultra-low energy circuit building blocks for security technologies. | Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy |
| 2018 | DATE | Exploiting on-chip power management for side-channel security. | Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay |
| 2017 | ISLPED | Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities. | Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay |
| 2017 | ISLPED | Invited paper: Ultra-low energy security circuit primitives for IoT platforms. | Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy |
| 2017 | ITC | Security keynote: Ultra-low-energy security circuit primitives for IoT platforms. | Sanu Mathew |
| 2016 | ARITH | Hardware Implementation of AES Using Area-Optimal Polynomials for Composite-Field Representation GF(2^4)^2 of GF(2^8). | Shay Gueron, Sanu Mathew |
| 2016 | ICCD | Ultra-low energy security circuits for IoT applications. | Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Ram Krishnamurthy |
| 2016 | ISLPED | Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines. | Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay |
| 2013 | ACSSC | Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers. | Andrew Carter, Paula Ning, William Koven, David Money Harris, Michael Braly, Nathan Jones, Julien Massas, Trevin Murakami, Alexandra Simoni, Sanu Mathew |
| 2013 | ARITH | Split-Path Fused Floating Point Multiply Accumulate (FPMAC). | Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy, Vasantha Erraguntla |
| 2011 | DAC | High-performance energy-efficient encryption in the sub-45nm CMOS Era. | Ram Krishnamurthy, Sanu Mathew, Farhana Sheikh |
| 2009 | VLSID | A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. | Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy |
| 2008 | VLSID | A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. | Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron |
| 2005 | ARITH | An Improved Unified Scalable Radix-2 Montgomery Multiplier. | David Money Harris, Ram Krishnamurthy, Mark A. Anders, Sanu Mathew, Steven Hsu |
| 2003 | ARITH | Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. | Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy |