Saroja V. Siddamal
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2014–2025
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | HiPC | RISC-V Based SoC Design Featuring Fixed and Floating Point Units with Integrated FFT Accelerator for DSP Workloads. | Umer Kudachi, Saroja V. Siddamal, Shreevatsa Alawandi, Aishwarya Beedanal |
| 2023 | VLSID | Supply Noise and Peak Current Reduction in High-Speed Output Drivers. | Dharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal |
| 2021 | VLSID | High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone. | Dharmaray Nedalgi, Saroja V. Siddamal |
| 2019 | VLSID | Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter. | Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. Siddamal, Sujata S. Kotabagi, Nalini C. Iyer |
| 2014 | VLSID | Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology. | Narayan V. Sugur, Saroja V. Siddamal, Samba Sivam Vemala |