Sergei Devadze
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
18
Venues
10
Active years
2005–2019
Best venue rank
A
Where they publish
Papers
18 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | IOLTS | Application Specific True Critical Paths Identification in Sequential Circuits. | Lembit Jrimgi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran |
| 2017 | ITC | Marginal PCB assembly defect detection on DDR3/4 memory bus. | Sergei Odintsov, Artur Jutman, Sergei Devadze |
| 2016 | ETS | On coverage of timing related faults at board level. | Artur Jutman, Igor Aleksejev, Sergei Devadze |
| 2016 | FDL | Designing reliable cyber-physical systems overview associated to the special session at FDL'16. | Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Grschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Knighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Rck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao |
| 2016 | ITC | A suite of IEEE 1687 benchmark networks. | Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath |
| 2015 | DATE | Fault simulation with parallel exact critical path tracing in multiple core environment. | Maksim Gorev, Raimund Ubar, Sergei Devadze |
| 2015 | ISCAS | Combinational fault simulation in sequential circuits. | Raimund Ubar, Jaak Kousaar, Maksim Gorev, Sergei Devadze |
| 2014 | DSD | Critical Path Tracing Based Simulation of Transition Delay Faults. | Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik |
| 2012 | ETS | Embedded synthetic instruments for Board-Level testing. | Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel |
| 2012 | ITC | FPGA-based synthetic instrumentation for board test. | Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel |
| 2011 | DSD | SoC and Board Modeling for Processor-Centric Board Testing. | Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze |
| 2010 | DATE | Parallel X-fault simulation with critical path tracing technique. | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2010 | DSD | Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. | Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2010 | IDC | Collaborative Distributed Fault Simulation for Digital Electronic Circuits. | Eero Ivask, Sergei Devadze, Raimund Ubar |
| 2009 | ITC | Fast extended test access via JTAG and FPGAs. | Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar |
| 2008 | ASPDAC | Parallel fault backtracing for calculation of fault coverage. | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2007 | ETS | Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
| 2005 | EDCC | Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. | Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman |