| 2025 | ISCAS | A 40 Gb/s Adaptive CTLE Using a Sub-Sampled PAM-4 Clock Recovery Circuit in 65nm CMOS. | Alok Kumar, Ishan Mishra, Tejavanth Kothani, Rajshekhar Mukherjee, Midhun V, Shalabh Gupta |
| 2024 | VLSID | Power Integrity Analysis for Interoperability of BoW Chiplet Interfaces. | Ishan Mishra, Jayaprakash Balachandran, Wen-Sin Liew, Elad Alon, Srinivas Venkataraman, Shalabh Gupta |
| 2024 | VLSID | A Compact Low-Power 29 Gb/s Pseudo Random Quaternary Sequence Generator in 65 nm CMOS. | Ishan Mishra, Ganpat Anant Parulekar, Shalabh Gupta |
| 2022 | ISCAS | A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM. | Zeeshan Ali, Pallavi Paliwal, Rupesh Lad, Dhanraj Bhukya, Shalabh Gupta |
| 2021 | VLSID | A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology. | Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta |
| 2021 | VLSID | A 27S/32S DC-balanced line coding scheme for PAM-4 signaling. | Miryala Chandra Shekar, Sandeep Goyal, Shalabh Gupta |
| 2019 | HOTI | Demonstration of a Single-Lane 80 Gbps PAM-4 Full-Duplex Serial Link. | Sandeep Goyal, Pranav Agarwal, Shalabh Gupta |
| 2019 | ISCAS | A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector. | Arun Goyal, Souvik Ghosh, Sandeep Goyal, Pallavi Paliwal, Shalabh Gupta |
| 2018 | ISCAS | A PAM-4 10S/12S line coding scheme with equi-probable levels. | Sandeep Goyal, Ron Joseph, Virendra Singh, Shalabh Gupta |
| 2018 | VLSID | A Quadrature-Phase Voltage Controlled Oscillator for Offset Phase and Frequency Compensation. | Pragya Maheshwari, Sadhu Pavan Kumar, Mukesh Deharia, Nandakumar Nambath, Shalabh Gupta |
| 2017 | VLSID | Frequency Enhancement in Miller Divider with Injection-Locking Portrait. | Mohammed Umar Shaikh, Sivaramakrishna Rudrapati, Nandish Bharat Thaker, Shalabh Gupta |
| 2016 | VLSID | Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical Receiver. | Saurabh R. Anmadwar, Nandakumar Nambath, Shalabh Gupta |
| 2016 | VLSID | A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE. | Pragya Maheshwari, Suhas Kaushik, Mahendra Sakare, Shalabh Gupta |
| 2016 | VLSID | A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. | Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta |
| 2015 | ICRA | Decentralized smart sensor scheduling for multiple target tracking for border surveillance. | James Zachary Hare, Shalabh Gupta, James Wilson |
| 2015 | ICRA | Human activity recognition using LZW-Coded Probabilistic Finite State Automata. | James Wilson, Nayeff Najjar, James Zachary Hare, Shalabh Gupta |
| 2015 | VLSID | A Wide Tuning Range LC Quadrature Phase Oscillator Employing Mode Switching. | Sivaramakrishna Rudrapati, Sharayu Jagtap, Mohammed Umar Shaikh, Shalabh Gupta |
| 2014 | ISCAS | A high-speed PRBS generator using flip-flops employing feedback for distributed equalization. | Mahendra Sakare, Shalabh Gupta |
| 2014 | VLSID | On Dependence of Amplitude Noise versus Offset Frequency in LC Oscillators. | Sivaramakrishna Rudrapati, Shalabh Gupta |
| 2012 | VLSID | Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS. | Pawan Kumar Moyade, Nandakumar Nambath, Allmin Ansari, Shalabh Gupta |
| 2012 | VLSID | Buffer Design and Eye-Diagram Based Characterization of a 20 GS/s CMOS DAC. | Mohit Singh, Shalabh Gupta |
| 2011 | DATE | Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping". | Mohit Singh, Mahendra Sakare, Shalabh Gupta |
| 2011 | FUSION | Multimodal sensor fusion for personnel detection. | Xin Jin, Shalabh Gupta, Asok Ray, Thyagaraju Damarla |
| 2007 | ACC | Estimation of Fatigue Life Using Ultrasonic Sensing: A Symbolic Dynamics Approach. | Shalabh Gupta, Asok Ray |
| 2007 | ACC | Irreversibility-based Measure of Slowly Evolving Anomalies. | Abhishek Srivastav, Asok Ray, Shalabh Gupta |