Shantanu Sarangi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
13
Venues
3
Active years
2011–2026
Best venue rank
National
Where they publish
Papers
13 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | VTS | Next-Gen Scalable In-System-Test Architecture for Nvidia Automotive Platform. | Sailendra Chadalavada, Milind Sonawane, Saranyan Sarangan, Alex Hsu, Pavan Javvaji, Shantanu Sarangi |
| 2024 | ITC | A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS. | Kunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun |
| 2022 | VTS | On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST). | Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz |
| 2022 | VTS | NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. | Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey |
| 2019 | ITC | An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. | Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn |
| 2019 | VTS | A Novel Graph Coloring Based Solution for Low-Power Scan Shift. | Saurabh Gupta, Bonita Bhaskaran, Shantanu Sarangi, Ayub Abdollahian, Jennifer Dworak |
| 2019 | VTS | Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms. | Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang |
| 2019 | VTS | Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency. | Milind Sonawane, Venkat Abilash Reddy Nerallapally, Alex Hsu, Shantanu Sarangi |
| 2017 | VTS | At-speed capture global noise reduction & low-power memory test architecture. | Bonita Bhaskaran, Sailendra Chadalavada, Shantanu Sarangi, Nithin Valentine, Venkat Abilash Reddy Nerallapally, Ayub Abdollahian |
| 2016 | ITC | Advanced test methodology for complex SoCs. | Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian |
| 2016 | VTS | Flexible scan interface architecture for complex SoCs. | Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn |
| 2016 | VTS | Dynamic docking architecture for concurrent testing and peak power reduction. | Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha |
| 2011 | DATE | A clock-gating based capture power droop reduction methodology for at-speed scan testing. | Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu |