| 2026 | DATE | DAPO: Design Structure-Aware Pass Ordering for HLS via Contrastive and Reinforcement Learning. | Jinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu, Wei Zhang |
| 2026 | FCCM | AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs. | Xiaofeng Zhou, Linfeng Du, Guangyu Hu, Sharad Sinha, Hongce Zhang, Wei Zhang |
| 2025 | DATE | UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE. | Yuying Zhang, Sharad Sinha, Jiang Xu, Wei Zhang |
| 2025 | FPGA | TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. | Enlai Li, Zhe Lin, Sharad Sinha, Wei Zhang |
| 2025 | PIMRC | Deep Learning Aided Low Latency Hybrid Beamforming with Selective Antenna Grouping. | Nikita Rathor, Neelakandan Rajamohan, Sharad Sinha |
| 2024 | FPGA | GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. | Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang |
| 2023 | DATE | Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs. | Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang |
| 2023 | FCCM | Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform. | Yuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang |
| 2023 | FPGA | FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. | Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang |
| 2023 | HiPC | Message from Workshop Chairs. | Sheikh K. Ghafoor, Sushil K. Prasad, Ashish Kuvelkar, Sharad Sinha, Satish Puri |
| 2022 | ICCAD | Attack Directories on ARM big.LITTLE Processors. | Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang |
| 2021 | DAC | Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict. | Zili Kou, Wenjian He, Sharad Sinha, Wei Zhang |
| 2021 | ICCAD | AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. | Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang |
| 2020 | ASPDAC | HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. | Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang |
| 2020 | ASPDAC | iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU. | Wenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das |
| 2020 | FPL | FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. | Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen |
| 2019 | DAC | LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. | Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang |
| 2019 | DATE | Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. | Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang |
| 2019 | FCCM | Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. | Zhe Lin, Sharad Sinha, Wei Zhang |
| 2019 | FPGA | A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. | Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang |
| 2019 | ICCAD | Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. | Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang |
| 2018 | FCCM | CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. | Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang |
| 2018 | FPL | A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. | Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha |
| 2017 | FPL | PAAS: A system level simulator for heterogeneous computing architectures. | Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang |
| 2017 | FPL | Decision tree based hardware power monitoring for run time dynamic power management in FPGA. | Zhe Lin, Wei Zhang, Sharad Sinha |
| 2017 | ICCAD | A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. | Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang |
| 2017 | ICCAD | COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. | Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He |
| 2016 | FPL | HeteroSim: A heterogeneous CPU-FPGA simulator. | Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang |
| 2015 | FPL | Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. | Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang |
| 2015 | FPL | Hierarchical library based power estimator for versatile FPGAs. | Hao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen, Hai Li |
| 2012 | FPL | Dataflow graph partitioning for high level synthesis. | Sharad Sinha, Thambipillai Srikanthan |