| 2024 | COMPSAC | Enhancing Security of Generalization Methods Based on m-Invariance for Dynamic Data Publication. | Fusu Zhang, Yoko Kamidoi, Shin'ichi Wakabayashi |
| 2022 | COMPSAC | Introduction of a New Method for Preventing Recipient Unapproved Transactions to Bitcoin Wallet. | Chuki Hayama, Yoko Kamidoi, Shin'ichi Wakabayashi |
| 2020 | COMPSAC | A Framework for Fast MapReduce Processing Considering Sensitive Data on Hybrid Clouds. | Shun Kawamoto, Yoko Kamidoi, Shin'ichi Wakabayashi |
| 2020 | COMPSAC | A Verifiable Secret Sharing Scheme without Using Multi-Party Computations. | Takumi Makino, Yoko Kamidoi, Shin'ichi Wakabayashi |
| 2019 | COMPSAC | A Protocol for Preventing Transaction Commitment without Recipient's Authorization on Blockchain. | Ryosuke Yamauchi, Yoko Kamidoi, Shin'ichi Wakabayashi |
| 2018 | DEXA | An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing. | Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi |
| 2018 | DSD | Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection. | Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi |
| 2013 | DSD | A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions. | Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi |
| 2013 | DSD | A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA. | Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi |
| 2011 | DSD | A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations. | Satoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi |
| 2011 | FPL | An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. | Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama |
| 2007 | PDPTA | A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning. | Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama |
| 2006 | ICDE | A Decision Method of Attribute Importance for Classification by Outlier Detection. | Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 2005 | ICDE | An Algorithm for Computing Global-Based Outlier Degrees on Data Sets. | Takeshi Fushimi, Yoko Kamidoi, Shin'ichi Wakabayashi |
| 2005 | ICDE | Feature Extraction of Clusters Based on FlexDice. | Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 2004 | FPL | An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. | Shin'ichi Wakabayashi, Kenji Kikuchi |
| 2000 | ASPDAC | Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. | Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi |
| 2000 | ASPDAC | Genetic algorithm accelerator GAA-II. | Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno |
| 2000 | ISCAS | An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. | Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi |
| 1999 | ASPDAC | Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. | Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide |
| 1999 | ASPDAC | An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. | Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta |
| 1998 | ASPDAC | A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. | Tetsushi Koide, Shin'ichi Wakabayashi |
| 1998 | PPSN | Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. | Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide |
| 1997 | ASPDAC | Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. | Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru |
| 1995 | ASPDAC | A new system partitioning method under performance and physical constraints for multi-chip modules. | Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 1995 | ASPDAC | A new performance driven placement method with the Elmore delay model for row based VLSIs. | Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru |
| 1995 | ASPDAC | A three-layer over-cell multi-channel routing method for a new cell model. | Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 1995 | ISCAS | An MCM Routing Algorithm Considering Crosstalk. | Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida |
| 1995 | ISCAS | A Verification Algorithm for Logic Circuits with Internal Variables. | Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida |
| 1994 | ISCAS | On Three-Way Graph Partitioning. | Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 1994 | ISCAS | A Floorplanning Method with Topological Constraint Manipulation. | Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
| 1994 | ISCAS | A Systolic Graph Partitioning Algorithm for VLSI Design. | Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida |
| 1993 | ISCAS | Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. | Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida |