| 2024 | ISCAS | Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator. | Lih-Yih Chiou, Hong-Ming Shih, Shun-Hsiu Hsu, Zu-Cheng Sheng, Soon-Jyh Chang |
| 2022 | ISCAS | A 12TOPS/W Computing-in-Memory Accelerator for Convolutional Neural Networks. | Jun-Hui Fu, Soon-Jyh Chang |
| 2021 | ISCAS | A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration. | Che-Wei Hsu, Soon-Jyh Chang |
| 2019 | ISCAS | A 2-GS/s 8b Flash-SAR Time-Interleaved ADC with Background Offset Calibration. | Yi-Shen Cheng, Huan-Jui Hu, Soon-Jyh Chang |
| 2019 | ISCAS | A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC. | Huan-Jui Hu, Yi-Shen Cheng, Soon-Jyh Chang |
| 2018 | ISCAS | A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window. | Chih-Yuan Kung, Chun-Po Huang, Chia-Chuan Li, Soon-Jyh Chang |
| 2017 | ISCAS | A 12-bit 40-MS/s calibration-free SAR ADC. | Chung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, Soon-Jyh Chang |
| 2017 | ISLPED | A low power duobinary voltage mode transmitter. | Ming-Hung Chien, Yen-Long Lee, Jih Ren Goh, Soon-Jyh Chang |
| 2016 | ASPDAC | A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. | Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin |
| 2016 | ISCAS | A pipeline ADC with latched-based ring amplifiers. | Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, Soon-Jyh Chang |
| 2015 | ISCAS | A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system. | Shuenn-Yuh Lee, Tzung-Min Tsai, Wei-Chih Lai, Soon-Jyh Chang, Stony Tai |
| 2015 | ISCAS | A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems. | Wei-Hao Tsai, Che-Hsun Kuo, Soon-Jyh Chang, Li-Tse Lo, Ying-Cheng Wu, Chun-Jen Chen |
| 2014 | ISCAS | A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window. | Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, Che-Hsun Kuo |
| 2014 | ISCAS | An area- and power-efficient half-rate clock and data recovery circuit. | Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Yen-Chi Chen, Jih Ren Goh, Chung-Ming Huang |
| 2013 | ISCAS | A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique. | I-Jen Chao, Chia-Ming Kuo, Bin-Da Liu, Chun-Yueh Huang, Soon-Jyh Chang |
| 2012 | ICCAD | Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. | Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang |
| 2012 | ISCAS | A power-efficient sizing methodology of SAR ADCs. | Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin |
| 2011 | DAC | Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. | Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang |
| 2010 | DAC | Performance-driven analog placement considering boundary constraint. | Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang |
| 2006 | ISCAS | A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique. | Jin-Fu Lin, Soon-Jyh Chang |
| 2006 | ISCAS | Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop. | Yen-Ting Liu, Lih-Yih Chiou, Soon-Jyh Chang |
| 1999 | ETS | A DFT for semi-DC fault diagnosis for switched-capacitor circuits. | Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen |
| 1997 | VTS | Functional test pattern generation for CMOS operational amplifier. | Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen |