Sorin Cotofana
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
34
Venues
17
Active years
1996–2025
Best venue rank
A*
Where they publish
Papers
34 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | A Convoluted Journey from CMOS to Spin Waves. | Pantazis Anagnostou, Arne Van Zegbroeck, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana |
| 2021 | DATE | Fan-out of 2 Triangle Shape Spin Wave Logic Gates. | Abdulqader Nael Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotofana, Florin Ciubotaru, Said Hamdioui |
| 2021 | ISCAS | Spin Wave Based Full Adder. | Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui |
| 2020 | DATE | n-bit Data Parallel Spin Wave Logic Gate. | Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui |
| 2020 | GECCO | Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA. | Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott |
| 2020 | ICCD | 4-output Programmable Spin Wave Logic Gate. | Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana |
| 2020 | ISCAS | Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case. | Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis |
| 2016 | DSD | Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units. | Thien Truong Nguyen-Ly, Tushar Gupta, Manuel Pezzin, Valentin Savin, David Declercq, Sorin Cotofana |
| 2015 | DATE | Hybrid adaptive clock management for FPGA processor acceleration. | Alexandru Gheolbanoiu, Lucian Petrica, Sorin Cotofana |
| 2015 | ICCD | ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits. | Satish Grandhi, David McCarthy, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana |
| 2014 | MICRO | Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs. | Changlin Chen, Sorin Cotofana |
| 2012 | SCOPES | Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms. | Anca Mariana Molnos, Ashkan Beyranvand Nejad, Ba Thang Nguyen, Sorin Cotofana, Kees Goossens |
| 2009 | ISCAS | An O(n) Residue Number System to Mixed Radix Conversion Technique. | Kazeem Alagbe Gbolagade, Sorin Cotofana |
| 2006 | ICINCO | Consciousness for modeling intelligence - simulating the evolution by closure to the inverse. | Tudor Niculiu, Cristian Lupu, Sorin Cotofana |
| 2006 | ISCAS | Electron counting based high-radix multiplication in single electron tunneling technology. | Cor Meenderinck, Sorin Cotofana |
| 2004 | CGI | Efficient Hardware for Antialiasing Coverage Mask Generation. | Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha |
| 2004 | DATE | GRAAL - A Development Framework for Embedded Graphics Accelerators. | Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha |
| 2004 | DATE | Compositional Memory Systems for Data Intensive Applications. | Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven |
| 2004 | ISCAS | Low cost and latency embedded 3D graphics reciprocation. | Dan Crisu, Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha |
| 2003 | ARITH | On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge. | Sorin Cotofana, Casper Lageweg, Stamatis Vassiliadis |
| 2003 | ISCAS | Design and experimental results of a CMOS flip-flop featuring embedded threshold logic. | Marius Padure, Sorin Cotofana, Stamatis Vassiliadis |
| 2003 | IWANN | A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. | Peter Celinski, Sorin Cotofana, Derek Abbott |
| 2003 | IWANN | CMOS Implementation of Generalized Threshold Functions. | Marius Padure, Sorin Cotofana, Stamatis Vassiliadis |
| 2003 | PACT | D-SAB: A Sparse Matrix Benchmark Suite. | Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana |
| 2002 | FCCM | MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. | Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers |
| 2002 | FPL | Field-Programmable Custom Computing Machines - A Taxonomy -. | Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers |
| 2001 | EuroPar | Topic 15+20: Multimedia and Embedded Systems. | Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana |
| 2001 | FCCM | An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia. | Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers |
| 2001 | FPL | The MOLEN rho-mu-Coded Processor. | Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana |
| 2001 | ICCD | MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. | Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers |
| 2001 | PDP | Coarse Reconfigurable Multimedia Unit Extension. | Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis |
| 2000 | EuroPar | Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note). | Marian Stanca, Stamatis Vassiliadis, Sorin Cotofana, Henk Corporaal |
| 1999 | EuroPar | Vector ISA Extension for Sparse Matrix-Vector Multiplication. | Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis |
| 1996 | ICANN | Serial Binary Addition with Polynominally Bounded Weights. | Sorin Cotofana, Stamatis Vassiliadis |