| 2007 | ITC | Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. | Soumitra Bose, Vishwani D. Agrawal |
| 2007 | ITC | Delay fault simulation with bounded gate delay mode. | Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal |
| 2007 | VTS | Delay Test Quality Evaluation Using Bounded Gate Delays. | Soumitra Bose, Vishwani D. Agrawal |
| 2006 | ITC | Fault Coverage Estimation for Non-Random Functional Input Sequences. | Soumitra Bose, Vishwani D. Agrawal |
| 2006 | VTS | Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. | Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram |
| 2004 | DATE | Extraction of Schematic Array Models for Memory Circuits. | Soumitra Bose, Amit Nandi |
| 2002 | DATE | Automated Modeling of Custom Digital Circuits for Test. | Soumitra Bose |
| 1997 | ITC | Algorithms for Switch Level Delay Fault Simulation. | Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski |
| 1993 | ITC | Generation of Compact Delay Tests by Multiple-Path Activation. | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal |
| 1993 | VLSID | A Path Delay Fault Simulator for Sequential Circuits. | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal |
| 1992 | DAC | Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. | Soumitra Bose, Prathima Agrawal |
| 1989 | ICCD | Verifying pipelined hardware using symbolic logic simulation. | Soumitra Bose, Allan L. Fisher |
| 1989 | LICS | PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses | Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov |
| 1988 | CADE | PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. | P. E. Allen, Soumitra Bose, Edmund M. Clarke, Spiro Michaylov |