| 2025 | VLSID | A Low-Power, Low-Noise, High-Performance Re-Convergent Clock Mesh Design for Large AI Compute Clusters. | Harivinay Kancharla, Sounil Biswas |
| 2016 | ITC | SERDES external loopback test using production parametric-test hardware. | Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi |
| 2014 | VTS | Innovative practices session 5C: Machine learning and data analysis in test. | Sounil Biswas, John M. Carulli, Dragoljub Gagi Drmanac, Arpan Bhattacherjee |
| 2009 | VTS | Maintaining Accuracy of Test Compaction through Adaptive Re-learning. | Sounil Biswas, Ronald D. Blanton |
| 2008 | ITC | Improving the Accuracy of Test Compaction through Adaptive Test Update. | Sounil Biswas, Ronald D. Blanton |
| 2008 | VTS | Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. | Sounil Biswas, R. D. (Shawn) Blanton |
| 2005 | DATE | Specification Test Compaction for Analog Circuits and MEMS. | Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi |
| 2004 | VTS | Generalized Sensitization using Fault Tuples. | Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton |
| 2003 | VLSID | A Path Sensitization Technique for Testing of Switched Capacitor Circuits. | Sounil Biswas, Baquer Mazhari |