Srinath R. Naidu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2001–2015
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | VLSID | Geometric Programming Formulation for Gate Sizing with Pipelining Constraints. | Srinath R. Naidu |
| 2007 | DATE | Use of statistical timing analysis on real designs. | A. Nardi, Emre Tuncer, Srinath R. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song |
| 2007 | VLSID | Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits. | Srinath R. Naidu |
| 2003 | DAC | Statistical timing for parametric yield prediction of digital integrated circuits. | Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah |
| 2002 | VLSID | Timing Yield Calculation Using an Impulse-Train Approach. | Srinath R. Naidu |
| 2001 | DATE | Minimizing stand-by leakage power in static CMOS circuits. | Srinath R. Naidu, E. T. A. F. Jacobs |