| 2026 | ETS | TDDB Stress Test Coverage Quantification using Cell-aware Transistor State Stress Model. | Vladimir A. Zivkovic, Stephan Eggersgl, Andreas Glowatz, Daniel Tille |
| 2024 | ITC | A Cell-aware Transistor State Stress Model and its Application for Quality Measurement. | Stephan Eggersgl, Andreas Glowatz |
| 2021 | ITC | On Reduction of Deterministic Test Pattern Sets. | Stephan Eggersgl, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer |
| 2019 | ETS | Machine Learning-based Prediction of Test Power. | Harshad Dhotre, Stephan Eggersgl, Krishnendu Chakrabarty, Rolf Drechsler |
| 2019 | ITC | Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. | Stephan Eggersgl |
| 2019 | ITC | IEEE European Test Symposium (ETS). | Stephan Eggersgl, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu |
| 2018 | ASPDAC | Approximation-aware testing for approximate circuits. | Arun Chandrasekharan, Stephan Eggersgl, Daniel Groe, Rolf Drechsler |
| 2018 | DDECS | Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. | Harshad Dhotre, Stephan Eggersgl, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen |
| 2017 | DATE | Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. | Sebastian Huhn, Stephan Eggersgl, Krishnendu Chakrabarty, Rolf Drechsler |
| 2017 | ETS | Foreword. | Maria K. Michael, Rolf Drechsler, Stephan Eggersgl, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken |
| 2016 | ETS | SAT-based post-processing for regional capture power reduction in at-speed scan test generation. | Stephan Eggersgl, Kohei Miyase, Xiaoqing Wen |
| 2016 | ETS | VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. | Sebastian Huhn, Stephan Eggersgl, Rolf Drechsler |
| 2015 | ETS | Compact test set generation for test compression-based designs. | Stephan Eggersgl |
| 2014 | ETS | Optimization-based multiple target test generation for highly compacted test sets. | Stephan Eggersgl, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler |
| 2013 | ICCAD | Improved SAT-based ATPG: more constraints, better compaction. | Stephan Eggersgl, Robert Wille, Rolf Drechsler |
| 2012 | DDECS | A new SAT-based ATPG for generating highly compacted test sets. | Stephan Eggersgl, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| 2011 | DATE | As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. | Stephan Eggersgl, Rolf Drechsler |
| 2010 | ETS | Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. | Daniel Tille, Stephan Eggersgl, Rene Krenz-Baath, Jrgen Schlffel, Rolf Drechsler |
| 2010 | ISCAS | Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. | Stephan Eggersgl, Daniel Tille, Rolf Drechsler |
| 2009 | ETS | Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. | Stephan Eggersgl, Rolf Drechsler |
| 2009 | ICCAD | Timing Arc based logic analysis for false noise reduction. | Murthy Palla, Jens Bargfrede, Stephan Eggersgl, Walter Anheier, Rolf Drechsler |
| 2007 | ISCAS | SAT-based ATPG for Path Delay Faults in Sequential Circuits. | Stephan Eggersgl, Grschwin Fey, Rolf Drechsler |
| 2007 | MEMOCODE | Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. | Stephan Eggersgl, Grschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jrgen Schlffel |