| 2014 | FPL | Source-level debugging for FPGA high-level synthesis. | Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson |
| 2014 | FPL | Modulo SDC scheduling with recurrence minimization in high-level synthesis. | Andrew Canis, Stephen Dean Brown, Jason Helge Anderson |
| 2013 | DATE | Multi-pumping for resource reduction in FPGA high-level synthesis. | Andrew Canis, Jason Helge Anderson, Stephen Dean Brown |
| 2013 | FPGA | High-level synthesis with LegUp: a crash course for users and researchers. | Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi |
| 2009 | FPGA | Towards automated ECOs in FPGAs. | Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour |
| 2008 | DAC | Functionally linear decomposition and synthesis of logic circuits for FPGAs. | Tomasz S. Czajkowski, Stephen Dean Brown |
| 2008 | FPL | Fast toggle rate computation for FPGA circuits. | Tomasz S. Czajkowski, Stephen Dean Brown |
| 2007 | ASPDAC | BddCut: Towards Scalable Symbolic Cut Enumeration. | Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown |
| 2007 | DAC | Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. | Tomasz S. Czajkowski, Stephen Dean Brown |
| 2006 | FCCM | A Multithreaded Soft Processor for SoPC Area Reduction. | Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown |
| 2006 | FPL | Modular Partitioning for Incremental Compilation. | Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry P. Borer |
| 2006 | FPL | Adaptive FPGAs: High-Level Architecture and a Synthesis Method. | Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic |
| 2006 | ICCAD | Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. | Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown |
| 2005 | DAC | FPGA technology mapping: a study of optimality. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | DAC | Incremental retiming for FPGA physical synthesis. | Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown |
| 2005 | FPL | FPGA PLB Evaluation using Quantified Boolean Satisfiability. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | FPL | Post-Placement BDD-Based Decomposition for FPGAs. | Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown |
| 2005 | SAT | FPGA Logic Synthesis Using Quantified Boolean Satisfiability. | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
| 2003 | FPGA | Recursive circuit clustering for minimum delay and area. | Mehrdad Eslami Dehkordi, Stephen Dean Brown |
| 2002 | FPGA | Integrated retiming and placement for field programmable gate arrays. | Deshanand P. Singh, Stephen Dean Brown |
| 2002 | FPGA | Constrained clock shifting for field programmable gate arrays. | Deshanand P. Singh, Stephen Dean Brown |
| 2002 | FPL | Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. | Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic |
| 2002 | ICCAD | Incremental placement for layout driven optimizations on FPGAs. | Deshanand P. Singh, Stephen Dean Brown |
| 2001 | FPGA | The case for registered routing switches in field programmable gate arrays. | Deshanand P. Singh, Stephen Dean Brown |
| 1998 | DAC | Technology Mapping for Large Complex PLDs. | Jason Helge Anderson, Stephen Dean Brown |
| 1998 | FPGA | An LPGA with Foldable PLA-style Logic Blocks. | Jason Helge Anderson, Stephen Dean Brown |