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Steven M. Nowick

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

44

Venues

8

Active years

1989–2019

Best venue rank

A*

Where they publish

Papers

44 indexed papers, newest first.

YearVenueTitleAuthors
2019ISLPEDTowards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs.Kshitij Bhardwaj, Paolo Mantovani, Luca P. Carloni, Steven M. Nowick
2017DATEAn asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.Weiwei Jiang, Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, Wayne P. Burleson, Greg Sadowski
2016DACAchieving lightweight multicast in asynchronous networks-on-chip using local speculation.Kshitij Bhardwaj, Steven M. Nowick
2015DACA Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's.Weiwei Jiang, Kshitij Bhardwaj, Geoffray Lacourba, Steven M. Nowick
2015ICCDIncreasing reconfigurability with memristive interconnects.John Demme, Bipin Rajendran, Steven M. Nowick, Simha Sethumadhavan
2014ASPDACA low-latency asynchronous interconnection network with early arbitration resolution.Georgios Faldamis, Weiwei Jiang, Gennette Gill, Steven M. Nowick
2013DATEA transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.Alberto Ghiribaldi, Davide Bertozzi, Steven M. Nowick
2013ISLPEDRobust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control.Yu Chen, Mingoo Seok, Steven M. Nowick
2012ICCDDesigning pipelined delay lines with dynamically-adaptive granularity for low-energy applications.Christos Vezyrtzis, Yannis P. Tsividis, Steven M. Nowick
2011DATEA delay-insensitive bus-invert code and hardware support for robust asynchronous global communication.Melinda Y. Agyekum, Steven M. Nowick
2010DATEAn error-correcting unordered code and hardware support for robust asynchronous global communication.Melinda Y. Agyekum, Steven M. Nowick
2010ICCDPractical completion detection for 2-of-N delay-insensitive codes.Marco Cannizzaro, Weiwei Jiang, Steven M. Nowick
2007ASPDACOptimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation.Cheoljoo Jeong, Steven M. Nowick
2007ICCADAn efficient algorithm for time separation of events in concurrent systems.Peggy B. McGee, Steven M. Nowick
2005DACA lattice-based framework for the classification and design of asynchronous pipelines.Peggy B. McGee, Steven M. Nowick
2005ITCTest generation for ultra-high-speed asynchronous pipelines.Feng Shi, Yiorgos Makris, Steven M. Nowick, Montek Singh
2004DACFast hazard detection in combinational circuits.Cheoljoo Jeong, Steven M. Nowick
2002DACResynthesis and peephole transformations for the optimization of large-scale asynchronous systems.Tiberiu Chelcea, Steven M. Nowick
2002DATEA Burst-Mode Oriented Back-End for the Balsa Synthesis System.Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards
2002DATEHigh-Speed Non-Linear Asynchronous Pipelines.Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick
2001DACRobust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols.Tiberiu Chelcea, Steven M. Nowick
2001DACTransformations for the Synthesis and Optimization of Asynchronous Distributed Control.Michael Theobald, Steven M. Nowick
2001ICCDMOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines.Montek Singh, Steven M. Nowick
1999DACPractical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces.Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
1999ICCADOPTIMISTA: state minimization of asynchronous FSMs for optimum output logic.Robert M. Fuhrer, Steven M. Nowick
1997ICCADOPTIMIST: state minimization for optimal 2-level logic implementation.Robert M. Fuhrer, Steven M. Nowick
1997ICCDPractical Advances in Asynchronous Design.Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
1997ISLPEDSynthesis of low-power asynchronous circuits in a specified environment.Steven M. Nowick, Michael Theobald
1997VLSIDSynthesis for Logical Initializability of Synchronous Finite State Machines.Montek Singh, Steven M. Nowick
1996DACSynthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes.Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick
1996DACEspresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic.Michael Theobald, Steven M. Nowick, Tao Wu
1996ISLPEDConcurrency-oriented optimization for low-power asynchronous systems.Luis A. Plana, Steven M. Nowick
1996ITCSynthesis-for-Initializability of Asynchronous Sequential Machines.Montek Singh, Steven M. Nowick
1995ICCADEstimation and bounding of energy consumption in burst-mode control circuits.Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh
1995ICCADSymbolic hazard-free minimization and encoding of asynchronous finite state machines.Robert M. Fuhrer, Bill Lin, Steven M. Nowick
1995VLSIDSynthesis of asynchronous circuits for stuck-at and robust path delay fault testability.Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
1994ICCDUCLOCK: Automated Design of High-Peformance Unclocked State Machines.Steven M. Nowick, Bill Coates
1992ICCADExact two-level minimization of hazard-free logic with multiple-input changes.Steven M. Nowick, David L. Dill
1992ICCDPractical Asynchronous Controller Design.Steven M. Nowick, Kenneth Y. Yun, David L. Dill
1992ICCDSynthesis of 3D Asynchronous State Machines.Kenneth Y. Yun, David L. Dill, Steven M. Nowick
1991ICCADAutomatic Synthesis of Locally-Clocked Asynchronous State Machines.Steven M. Nowick, David L. Dill
1991ICCDSynthesis of Asynchronous State Machines Using A Local Clock.Steven M. Nowick, David L. Dill
1989ICCADPracticality of state-machine verification of speed-independent circuits.Steven M. Nowick, David L. Dill
1989ICCDAutomatic verification of speed-independent circuits with Petri net specifications.David L. Dill, Steven M. Nowick, Robert F. Sproull