Skip to content

Sudip Nag

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

7

Active years

1992–2004

Best venue rank

A*

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2004FPLRun-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng
2000FPLA Placement Algorithm for FPGA Designs with Multiple I/O Standards.Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman
1999DATEPost-Placement Residual-Overlap Removal with Minimal Movement.Sudip Nag, Kamal Chaudhary
1999VLSIDVLSI Signal Processing in FPGAs.Sudip Nag, H. K. Verma, Kaushik Roy
1994DACPerformance-Driven Simultaneous Place and Route for Row-Based FPGAs.Sudip Nag, Rob A. Rutenbar
1994FPLOn Channel Architecture and Routability for FPGAs Under Faulty Conditions.Kaushik Roy, Sudip Nag
1994ISCASASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits.Santanu Dutta, Sudip Nag, Kaushik Roy
1993DACIterative Wirability and Performance Improvement for FPGAs.Sudip Nag, Kaushik Roy
1993ICCDChannel Architecture Optimization for Performance and Routability of Row-Based FPGAs.Kaushik Roy, Sudip Nag, Santanu Dutta
1992ICCADSystem-level routing of mixed-signal ASICs in WREN.Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley