Skip to content

Sudipta Paria

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

7

Active years

2025–2026

Best venue rank

A*

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2026DATECOVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events.Mahmudul Hasan, Sudipta Paria, Swarup Bhunia, Tamzidul Hoque
2026FPGAPROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros.Pravin Gaikwad, Aritra Dasgupta, Sudipta Paria, Peyman Dehghanzadeh, Jonathan Cruz, Swarup Bhunia
2026VTSVTS2026 Contest Publication: TTTC's E.J. McCluskey Best Doctoral Thesis Award.Luca Benini, Paolo Bernardi, Alberto Bosio, Swarup Bhunia, Riccardo Cantoro, Degang Chen, Krishnendu Chakrabarty, Jayeeta Chaudhuri, Bastien Deveautour, Gabriele Filipponi, Angelo Garofalo, Salvatore Pappalardo, Sudipta Paria, Michael Rogenmoser, Philippe Sauter, Michael Sekyere, Chen Wu
2026VTSExploring Agentic LLM Paradigms for Hardware Verification across Abstraction Levels.Sudipta Paria, Swarup Bhunia
2025DACPOLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage.Tanzim Mahfuz, Sudipta Paria, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty
2025ICCADPROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation.Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj P. D.
2025ICCDFV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation.Sudipta Paria, Aritra Dasgupta, Dinesh Reddy Ankireddy, Prabuddha Chakraborty, Swarup Bhunia
2025ITCLAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs.Sudipta Paria
2025ITCLITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency.Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia
2025VTSCLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking.Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia
2025VTSTowards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages.Sudipta Paria, Aritra Dasgupta, Swarup Bhunia