Suriyaprakash Natarajan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
31
Venues
6
Active years
1999–2025
Best venue rank
A*
Where they publish
Papers
31 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | DAC | Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems. | Sanjay Das, Swastik Bhattacharya, Anand Menon, Shamik Kundu, Pooja Madhusoodhanan, Prasanth Viswanathan Pillai, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu |
| 2025 | ITC | DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors. | Suriyaprakash Natarajan, Chaitali S. Oak, Nipun Chaplot, Vijay Kakollu, Venkata A. R. Gurram, Manish J. Mishra, Fayez Abu-gosh |
| 2025 | VTS | Innovation Practices Track: Frontiers in Diagnosis and Debug. | Suriyaprakash Natarajan, Saghir A. Shaikh, Wu-Tung Cheng, Sankaran Menon |
| 2025 | VTS | Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation. | Mehmet Onder, Lakshmanan Balasubramanian, Rubin A. Parekhji, Suriyaprakash Natarajan, Sule Ozev |
| 2024 | ITC | TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Hyperdimensional Clustering. | Suhasini Komarraju, Mohamed Mejri, Abhijit Chatterjee, Suriyaprakash Natarajan, Prashant Goteti |
| 2024 | ITC | Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor. | Suriyaprakash Natarajan, Chaitali S. Oak, Vijay Kakollu, Nipun Chaplot, Soham Roy, Apurva Lonkar, Gerardo J. Perfecto Reyes |
| 2024 | VTS | Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors. | Suhas Krishna Kashyap, Chinmaye Raghavendra, Suriyaprakash Natarajan, Sule Ozev |
| 2023 | ITC | Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits. | Ayush Arunachalam, Sanjay Das, Monikka Rajan, Fei Su, Xiankun Jin, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu |
| 2022 | DAC | A defect tolerance framework for improving yield. | Shiva Shankar Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris |
| 2022 | ITC | DEFCON: Defect Acceleration through Content Optimization. | Suriyaprakash Natarajan, Abhijit Sathaye, Chaitali Oak, Nipun Chaplot, Suvadeep Banerjee |
| 2021 | VTS | Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. | Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee |
| 2020 | ITC | SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. | Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee |
| 2020 | ITC | Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization. | Srikanth Venkataraman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang |
| 2020 | VTS | Automated Design For Yield Through Defect Tolerance. | Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen |
| 2016 | ASPDAC | Every test makes a difference: Compressing analog tests to decrease production costs. | Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan |
| 2016 | ITC | Fault simulation for analog test coverage. | Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary |
| 2016 | VTS | Infant mortality tests for analog and mixed-signal circuits. | Suvadeep Banerjee, Suriyaprakash Natarajan |
| 2016 | VTS | Session 4B - Panel data analytics in semiconductor manufacturing. | Suriyaprakash Natarajan, Li-C. Wang |
| 2015 | DATE | Fast eye diagram analysis for high-speed CMOS circuits. | Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan |
| 2014 | ITC | Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation. | Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli Jr., Yiorgos Makris |
| 2013 | ICCAD | Scalable and efficient analog parametric fault identification. | Mustafa Berke Yelten, Suriyaprakash Natarajan, Bin Xue, Prashant Goteti |
| 2013 | VTS | Special session 12B: Panel post-silicon validation & test in huge variance era. | Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas |
| 2011 | VTS | The buck stops with wafer test: Dream or reality? | Suriyaprakash Natarajan, Arani Sinha |
| 2011 | VTS | The bang for the buck with resiliency: Yield or field? | Arani Sinha, Suriyaprakash Natarajan |
| 2010 | ITC | Path coverage based functional test generation for processor marginality validation. | Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche |
| 2010 | VTS | Innovative practices session 9C: Implications of power delivery network for validation and testing. | Suriyaprakash Natarajan |
| 2008 | ITC | On Accelerating Path Delay Fault Simulation of Long Test Sequences. | I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta |
| 2006 | VTS | Path Delay Fault Simulation on Large Industrial Designs. | Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty |
| 2002 | ITC | XIDEN: Crosstalk Target Identification Framework. | Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer |
| 2001 | ITC | Switch-level delay test of domino logic circuits. | Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer |
| 1999 | ITC | Switch-level delay test. | Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer |